SC1200 datasheet(36/60 Pages) TI

36 / 60 page

MSC1200

SBAS289E

www.ti.com

IE5

External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be

bit 7

cleared manually by software. Setting this bit in software will cause an interrupt if enabled.

IE4

External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared

bit 6

manually by software. Setting this bit in software will cause an interrupt if enabled.

IE3

External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared

bit 5

manually by software. Setting this bit in software will cause an interrupt if enabled.

IE2

External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared

bit 4

manually by software. Setting this bit in software will cause an interrupt if enabled.

Configuration Address Register (CADDR) (write only)

Reset Value

SFR 94H

00H

Reset Value

SFR 93H

00H

CADDR

Configuration Address Register. This register supplies the address for reading bytes in the 64 bytes of Flash Configuration

bits 7-0

Memory. Always use the Boot ROM CADDR access routine. This register is also used for SFR read and write

routines.

WARNING: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.

Configuration Data Register (CDATA)

CDATA

Configuration Data Register. This register will contain the data in the 64 bytes of Flash Configuration Memory

bits 7-0

that is located at the last written address in the CADDR register. This is a read-only register.

Reset Value

SFR 91H

IE5

IE4

IE3

IE2

08H

External Interrupt Flag (EXIF)

SC1200 Datasheet(PDF) 36 Page - Texas Instruments

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