SC1200 datasheet(18/60 Pages) TI

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MSC1200

SBAS289E

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FIGURE 8. Filter Step Responses.

SETTLING TIME

FILTER

(Conversion Cycles)

Sinc3

3(1)

Sinc2

2(1)

Fast

1(1)

NOTE: (1) With Synchronized Channel Changes.

CONVERSION CYCLE

Discard

Fast

Sinc2

Sinc3

AUTO MODE FILTER SELECTION

FILTER SETTLING TIME

Adjustable Digital Filter

Data Out

Modulator

Fast Settling

Sinc2

Sinc3

RMS

FULL-SCALE

ENOB

MEASUREMENT

PGA

RANGE

AT 10Hz

RESOLUTION

SETTING

(V)

(BITS)

(nV)

±2.5

21.7

1468

±1.25

21.5

843

±0.625

21.4

452

±0.313

21.2

259

±0.156

20.8

171

±0.0781

20.4

113

±0.039

74.5

128

±0.019

74.5

TABLE I. ENOB Versus PGA.

PGA

The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.

Using the PGA can actually improve the effective resolution

of the ADC. For instance, with a PGA of 1 on a

±2.5V full-

scale range, the ADC can resolve to 1.5

µV. With a PGA of

128 on a

±19mV full-scale range, the ADC can resolve to

75nV. With a PGA of 1 on a

±2.5V full-scale range, it would

require a 26-bit ADC to resolve 75nV, as shown in Table I.

OFFSET DAC

The analog output from the PGA can be offset by up to half

the full-scale input range of the PGA by using the ODAC

bit value; the MSB is the sign and the seven LSBs provide

the magnitude of the offset. Since the ODAC introduces an

analog (instead of digital) offset to the PGA, using the ODAC

does not reduce the range of the ADC.

MODULATOR

The modulator is a single-loop 2nd-order system. The modu-

lator runs at a clock speed (fMOD) that is derived from the CLK

using the value in the Analog Clock register (ACLK, F6H).

The data output rate is:

Data Rate = fDATA =

Decimation Ratio

MOD

where fMOD =

ACLK

CLK

ACLK

()

+•

164

CALIBRATION

The offset and gain errors in the MSC1200, or the complete

system, can be reduced with calibration. Calibration is con-

trolled through the ADCON1 register (SFR DDH), bits

CAL2:CAL0. Each calibration process takes seven tDATA

periods (data conversion time) to complete. Therefore, it

takes 14 tDATA periods to complete both an offset and gain

calibration.

For system calibration, the appropriate signal must be

applied to the inputs. The system offset calibration requires a

zero-differential input signal. It then computes an offset value

that will nullify offset in the system. The system gain calibration

requires a positive full-scale differential input signal. It then

computes a gain value to nullify gain errors in the system.

Each of these calibrations will take seven tDATA periods to

complete.

Calibration should be performed after power on, a change in

temperature, power supply, voltage reference, decimation

ratio, buffer, or a change of the PGA. Calibration will remove

the effects of the Offset DAC; therefore, changes to the

Offset DAC register should be done after calibration.

At the completion of calibration, the ADC Interrupt bit goes

high, which indicates the calibration is finished and valid data

is available.

DIGITAL FILTER

The Digital Filter can use either the Fast Settling, Sinc2, or

Sinc3 filter, as shown in Figure 8. In addition, the Auto mode

changes the Sinc filter after the input channel or PGA is

changed. When switching to a new channel, it will use the

Fast Settling filter, for the next two conversions the first of

which should be discarded. It will then use the Sinc2 followed

by the Sinc3 filter to improve noise performance. This com-

bines the low-noise advantage of the Sinc3 filter with the

quick response of the Fast Settling Time filter. The frequency

response of each filter is shown in Figure 9.

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