SC1200 datasheet(35/60 Pages) TI

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MSC1200

SBAS289E

www.ti.com

Port 1 (P1)

Reset Value

SFR 90H

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

FFH

INT5

INT4

INT3

INT2/SS

DIN

DOUT

PROG

P1.7-0

General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have

bits 7-0

an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port

1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate

function, set the appropriate mode in P1DDRL (SFR AEH), P1DDRH (SFR AFH).

INT5

External Interrupt 5.A falling edge on this pin will cause an external interrupt 5 if enabled.

bit 7

INT4

External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled.

bit 6

INT3

External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled.

bit 5

INT2/SS

External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. This pin can be used

bit 4

as slave select (SS) in SPI slave mode.

DIN

Serial Data In. This pin receives serial data in SPI and I2C modes (in I2C mode, this pin should be configured

bit 3

as an input) or standard 8051.

DOUT

Serial Data Out. This pin transmits serial data in SPI and I2C modes (in I2C mode, this pin should be configured

bit 2

as an open drain) or standard 8051.

PROG

Program Mode. When this pin is pulled low at power-up, the device enters Serial Programming mode (refer to

bit 0

Figure B).

Timer 1 MSB (TH1)

Reset Value

SFR 8DH

TH1.7

TH1.6

TH1.5

TH1.4

TH1.3

TH1.2

TH1.1

TH1.0

00H

Reset Value

SFR 8EH

T1M

T0M

MD2

MD1

MD0

01H

TH1.7-0

Timer 1 MSB. This register contains the most significant byte of Timer 1.

bits 7-0

Clock Control (CKCON)

T1M

Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0

bit 4

maintains 8051 compatibility. This bit has no effect on instruction cycle timing.

0: Timer 1 uses a divide by 12 of the crystal frequency.

1: Timer 1 uses a divide by 4 of the crystal frequency.

T0M

Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0

bit 3

maintains 8051 compatibility. This bit has no effect on instruction cycle timing.

0: Timer 0 uses a divide by 12 of the crystal frequency.

1: Timer 0 uses a divide by 4 of the crystal frequency.

MD2, MD1, MD0 Stretch MOVX Select. These bits select the time by which MOVX cycles are to be stretched. Since the MSC1200

bit 3

does not allow external memory access, these bits should be set to 000B to allow for the fastest flash data memory

access.

Memory Write Select (MWS)

MXWS

MOVX Write Select. This allows writing to the internal Flash program memory.

bit 0

0: No writes are allowed to the internal Flash program memory.

1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on.

Reset Value

SFR 8FH

MXWS

00H

SC1200 Datasheet(PDF) 35 Page - Texas Instruments

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