MSC1200

27

SBAS289E

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Serial Flash Programming Mode

Two methods of programming are available: serial program-

ming mode and user application mode. Serial programming

POR, as shown in Figure 21. User Application mode also

allows for Flash programming. Code execution from Flash

Memory cannot occur in this mode while programming, but

code execution can occur from Boot ROM while programming.

INTERRUPT

INTERRUPT/EVENT

ADDR

NUM

PRIORITY

FLAG

ENABLE

CONTROL

HIGH

6

0

N/A

6

0

N/A

6

0

N/A

Milliseconds Timer

6

0

N/A

ADC

6

0

N/A

Summation Register

6

0

N/A

Seconds Timer

6

0

N/A

External Interrupt 0

0

1

PX0 (IP.0)

Timer 0 Overflow

1

2

PT0 (IP.1)

External Interrupt 1

2

3

PX1 (IP.2)

Timer 1 Overflow

3

4

PT1 (IP.3)

Serial Port 0

4

5

RI_0 (SCON0.0)

PS0 (IP.4)

TI_0 (SCON0.1)

External Interrupt 2

8

6

IE2 (EXIF.4)

PX2 (EIP.0)

External Interrupt 3

9

7

IE3 (EXIF.5)

PX3 (EIP.1)

External Interrupt 4

10

8

IE4 (EXIF.6)

PX4 (EIP.2)

External Interrupt 5

11

9

IE5 (EXIF.7)

PX5 (EIP.3)

Watchdog

12

10

WDTI (EICON.3)

PWDI (EIP.4)

LOW

NOTES: (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge triggered, cleared automatically by hardware when the

service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs.

(4) Globally enabled by EA (IE.7).

TABLE VII. Interrupt Summary.

INTERRUPT

INTERRUPTS

The MSC1200 uses a three-priority interrupt system. As

shown in Table VII, each interrupt source has an indepen-

dent priority bit, flag, interrupt vector, and enable (except that

nine interrupts share the Auxiliary Interrupt (AI) at the highest

priority). In addition, interrupts can be globally enabled or

disabled. The interrupt structure is compatible with the origi-

nal 8051 family. All of the standard interrupts are available.

HARDWARE CONFIGURATION MEMORY

The 64 configuration bytes can only be written during the

program mode. The bytes are accessed through SFR regis-

configuration bytes control Flash partitioning and system

control. If the security bit is set, these bits cannot be changed

except with a Mass Erase command that erases all of the

Flash Memory including the 64 configuration bytes.

FIGURE 21. Serial Programming Mode.

MSC1200

Programmer

P3.0/RxD0

P3.1/TxD0

P1.0/PROG

NOTE: For user application mode, avoid heavy loading on

P1.0/PROG, which may result in erroneously entering serial

programming mode on power-up.