SC1200 datasheet(26/60 Pages) TI

26 / 60 page

MSC1200

SBAS289E

www.ti.com

Working Registers

As part of the lower 128 bytes of RAM, there are four banks

of Working Registers, as shown in Figure 20. The Working

Registers are general-purpose RAM locations that can be

addressed in a special way. They are designated R0 through

R7. Since there are four banks, the currently selected bank will

be used by any instruction using R0-R7. This allows software

to change context by simply switching banks. This is controlled

via the Program Status Word register (PSW; 0D0H) in the SFR

area described below. The 16 bytes immediately above the

R0-R7 registers are bit addressable. So any of the 128 bits in

this area can be directly accessed using bit addressable

instructions.

Stack

Another use of the Scratchpad area is for the programmer’s

stack. This area is selected using the Stack Pointer (SP; 81H)

SFR. Whenever a call or interrupt is invoked, the return

address is placed on the Stack. It also is available to the

programmer for variables, etc., since the Stack can be

moved and there is no fixed location within the RAM desig-

nated as Stack. The Stack Pointer will default to 07H on reset.

The user can then move it as needed. The SP will point to the

last used value. Therefore, the next value placed on the

Stack is put at SP + 1. Each PUSH or CALL will increment

the SP by the appropriate value. Each POP or RET will

decrement as well.

Program Memory

After reset, the CPU begins execution from Program Memory

location 0000H. The standard internal Program Memory size for

MSC1200 family members is shown in Table V. If enabled the

Boot ROM will appear from address F800H to FBFFH.

STANDARD INTERNAL

MODEL NUMBER

PROGRAM MEMORY SIZE (BYTES)

MSC1200Y3

MSC1200Y2

TABLE V. MSC1200 Maximum Internal Program Memory Sizes.

Boot ROM

There is a 1kB Boot ROM that controls operation during serial

programming. Additionally, the Boot ROM routines shown in

Table VI can be accessed during the user mode if it is enabled.

When enabled, the Boot ROM routines will be located at

memory addresses F800H-FBFFH during user mode.

HEX ADDRESS

ROUTINE

C DECLARATIONS

DESCRIPTION

F802

sfr_rd

char sfr_rd(void);

Return SFR value pointed to by CADDR(1)

F805

sfr_wr

void sfr_wr(char d);

Write to SFR pointed to by CADDR(1)

FBD8

monitor_isr

void monitor_isr() interrupt 6;

Push registers and call cmd_parser

FBDA

cmd_parser

void cmd_parser(void);

See SBAA076B.pdf

FBDC

put_string

void put_string(char code *string);

Output string

FBDE

page_erase

char page_erase (int faddr, char fdata, char fdm);

Erase flash page

FBE0

write_flash

Assembly only; DPTR = address, ACC = data

Flash write(2)

FBE2

write_flash_chk

char write_flash_chk (int faddr, char fdata, char fdm);

Write flash byte, verify

FBE4

write_flash_byte

void write_flash_byte (int faddr, char fdata);

Write flash byte(2)

FBE6

faddr_data_read

char faddr_data_read(char faddr);

Read HW config byte from faddr

FBE8

data_x_c_read

char data_x_c_read(int faddr, char fdm);

Read xdata or code byte

FBEA

tx_byte

void tx_byte(char);

Send byte to USART0

FBEC

tx_hex

void tx_hex(char);

Send hex value to USART0

FBEE

putx

void putx(char);

Send “x” to USART0 on R7 = 1

FBF0

rx_byte

char rx_byte(void);

Read byte from USART0

FBF2

rx_byte_echo

char rx_byte_echo(void);

Read and echo byte on USART0

FBF4

rx_hex_echo

char rx_hex_echo(void);

Read and echo hex on USART0

FBF6

rx_hex_dbl_echo

int rx_hex_dbl_echo(void);

Read int as hex and echo: USART0

FBF8

rx_hex_word_echo

int rx_hex_word_echo(void);

Read int reversed as hex and echo: USART0

FBFA

autobaud

void autobaud(void);

Set baud with received CR(3)

FBFC

putspace1

void putspace1(void);

Output 1 space to USART0

FBFE

putcr

void putcr(void);

Output CR, LF to USART0

NOTES: (1) CADDR must be set using the faddr_data_read routine.

(2) MWS register (SFR 8FH) defines Data Memory or Program Memory write.

(3) SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00.

TABLE VI. MSC1200 Boot ROM Routines.

SC1200 Datasheet(PDF) 26 Page - Texas Instruments

SC1200 Datasheet(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL