SC1200 datasheet(52/60 Pages) TI

52 / 60 page

MSC1200

SBAS289E

www.ti.com

Low Voltage Detect Control (LVDCON)

ALVDIS

Analog Low Voltage Detect Disable.

bit 7

0 = Enable Detection of Low Analog Supply Voltage (ALVD interrupt set when AVDD < 2.8V).

1 = Disable Detection of Low Analog Supply Voltage.

Reset Value

SFR E7H

ALVDIS

8FH

Extended Interrupt Enable (EIE)

Reset Value

SFR E8H

EWDI

EX5

EX4

EX3

EX2

E0H

EWDI

Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by

the WDTCON (SFR FFH) and PDCON (SFR F1H) registers.

bit 4

0 = Disable the Watchdog Interrupt

1 = Enable Interrupt Request Generated by the Watchdog Timer

EX5

External Interrupt 5 Enable. This bit enables/disables external interrupt 5.

bit 3

0 = Disable External Interrupt 5

1 = Enable External Interrupt 5

EX4

External Interrupt 4 Enable. This bit enables/disables external interrupt 4.

bit 2

0 = Disable External Interrupt 4

1 = Enable External Interrupt 4

EX3

External Interrupt 3 Enable. This bit enables/disables external interrupt 3.

bit 1

0 = Disable External Interrupt 3

1 = Enable External Interrupt 3

EX2

External Interrupt 2 Enable. This bit enables/disables external interrupt 2.

bit 0

0 = Disable External Interrupt 2

1 = Enable External Interrupt 2

Offset DAC Register (ODAC)

ODAC

Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset

bit7-0

DAC value is summed with the ADC input prior to conversion. Writing 00H or 80H to ODAC turns off the Offset DAC.

bit 7

Offset DAC Sign bit.

0 = Positive

1 = Negative

bit 6-0

Offset =

−

•

• 







•−

PGA

ODAC

REF

bit

127

[: ]

()

NOTE: ODAC cannot be used to offset the input so that the buffer can be used for AGND signals.

Reset Value

SFR E6H

00H

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