PM8313 datasheet(102/192 Pages) PMC

102 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Bit

Type

Function

Default

Bit 7

RD7

Bit 6

RD6

Bit 5

RD5

Bit 4

RD4

Bit 3

RD3

Bit 2

RD2

Bit 1

RD1

Bit 0

RD0

RD0 corresponds to the first bit of the serial byte received by the RFDL.

This register is actually a 4 level FIFO. If data is available, the FE bit in the

Status register is low. If INTC[1:0] (in the Enable/Status register) is set to 01, the

Receive Data register must be read within 31 data bit periods to prevent an

overrun. If INTC[1:0] is set to 11 the Receiver Data register must be read within

15 data bit periods.

When an overrun is detected, an interrupt is generated and the FIFO is held

cleared until the Status register is read. When the LAPD abort sequence

(01111111) is detected in the data an ABORT interrupt is generated and the

data that has been shifted into the serial to parallel converter is written into the

FIFO.

A read of the Receive Data register increments the FIFO pointer at the end of the

read. If the Receive Data register read causes an FIFO underrun, then the

pointer is inhibited from incrementing. The underrun condition will be signaled in

the next Status read by returning all zeros.

PM8313 Datasheet(PDF) 102 Page - PMC-Sierra, Inc