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PM8313 Datasheet(PDF) 103 Page - PMC-Sierra, Inc |
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PM8313 Datasheet(HTML) 103 Page - PMC-Sierra, Inc |
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103 / 192 page ![]() PM8313 D3MX DATA SHEET PMC-920702 ISSUE 5 M13 MULTIPLEXER 93 Register 28H: MX23 Configuration Bit Type Function Default Bit7 Unused X Bit6 Unused X Bit5 Unused X Bit4 Unused X Bit3 R/W LBCODE[1] 0 Bit2 R/W LBCODE[0] 0 Bit1 R/W CBE 0 Bit0 R/W INTE 0 INTE: When set high, the INTE bit enables the MX23 to activate the interrupt output, INTB, whenever any of the LBRI[7:1] bits are set high in the MX23 Loopback Request Interrupt register. MX23 interrupts are masked when INTE is cleared low. CBE: When set high, the CBE bit enables C-bit parity operation. When CBE is low, M23 operation is enabled. While in C-bit parity mode, loopback request detection and loopback request insertion are disabled. The generated DS2 clock, GD2CLK, is nominally 6.3062723 MHz while in C-bit parity mode, received C bits are ignored, and transmitted C bits are set to 1. While in M23 mode, the generated DS2 clock, GD2CLK, is nominally 6.311993 MHz and C bit decoding and encoding is fully operational. LBCODE[1:0]: The LBCODE[1:0] bits select the valid state for a loopback request coded in the C-bits of the DS3 signals. Transmit and receive are not independent; the same code is expected in the receive DS3 as is inserted in the transmitted DS3. The following table gives the correspondence between LBCODE[1:0] bits and the valid codes: |
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