LAN8700 datasheet(42/74 Pages) MICROCHIP

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LAN8700/LAN8700i

DS00002260A-page 42

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5.4

Miscellaneous Functions

5.4.1

CARRIER SENSE

The carrier sense is output on CRS. CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The

PHY asserts CRS based only on receive activity whenever the PHY is either in repeater mode or full-duplex mode. Oth-

erwise the PHY asserts CRS based on either transmit or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier

sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 con-

secutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is

asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after

the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE

followed by some non-IDLE symbol.

5.4.2

COLLISION DETECT

A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate

that a collision has been detected. COL remains active for the duration of the collision. COL is changed asynchronously

to both RX_CLK and TX_CLK. The COL output becomes inactive during full duplex mode.

COL may be tested by setting register 0, bit 7 high. This enables the collision test. COL will be asserted within 512 bit

times of TX_EN rising and will be de-asserted within 4 bit times of TX_EN falling.

In 10M mode, COL pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de-assertion of

TX_EN). This is the Signal Quality Error (SQE) signal and indicates that the transmission was successful. The user can

disable this pulse by setting bit 11 in register 27.

5.4.3

ISOLATE MODE

The PHY data paths may be electrically isolated from the MII by setting register 0, bit 10 to a logic one. In isolation mode,

the PHY does not respond to the TXD, TX_EN and TX_ER inputs. The PHY still responds to management transactions.

Isolation provides a means for multiple PHYs to be connected to the same MII without contention occurring. The PHY

is not isolated on power-up (bit 0:10 = 0).

TABLE 5-47:

ALTERNATIVE INTERRUPT SYSTEM MANAGEMENT TABLE

Mask

Interrupt Source Flag

Interrupt Source

Event to Assert

nINT

Condition to

De-Assert.

Bit to Clear

nINT

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1

17.1 low

29.7

30.6

29.6

Auto-Negotiation

complete

1.5

Auto-Negotiate

Complete

Rising 1.5

1.5 low

29.6

30.5

29.5

Remote Fault Detected

1.4

Remote Fault

Rising 1.4

1.4 low

29.5

30.4

29.4

Link Down

1.2

Link Status

Falling 1.2

1.2 high

29.4

30.3

29.3

Auto-Negotiation LP

Acknowledge

5.14

Acknowledge

Rising 5.14

5.14 low

29.3

30.2

29.2

Parallel Detection Fault

6.4

Parallel Detection Fault

Rising 6.4

6.4 low

29.2

30.1

29.1

Auto-Negotiation Page

Received

6.1

Page Received

Rising 6.1

6.1 low

29.1

Note:

The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the

Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is present, then both 17.1 and 29.7

will clear within a few milliseconds.

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