LAN8700 datasheet(14/74 Pages) MICROCHIP

14 / 74 page

LAN8700/LAN8700i

DS00002260A-page 14

 2007-2016 Microchip Technology Inc.

4.0

ARCHITECTURE DETAILS

4.1

Top Level Functional Architecture

Functionally, the PHY can be divided into the following sections:

• 100Base-TX transmit and receive

• 10Base-T transmit and receive

• MII or RMII interface to the controller

• Auto-negotiation to automatically determine the best speed and duplex possible

• Management Control to read status registers and write control registers

4.2

100Base-TX Transmit

The data path of the 100Base-TX is shown in Figure 4-1. Each major block is explained below.

4.2.1

100M TRANSMIT DATA ACROSS THE MII/RMII INTERFACE

For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid data. The

data is latched by the PHY’s MII block on the rising edge of TX_CLK. The data is in the form of 4-bit wide 25MHz data.

The MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid data. The data is

latched by the PHY’s MII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50MHz data.

4.2.2

4B/5B ENCODING

The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles to 5-

bit symbols (known as “code-groups”) according to Table 4-1. Each 4-bit data-nibble is mapped to 16 of the 32 possible

code-groups. The remaining 16 code-groups are either used for control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The

remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is

/I/, a transmit error code-group is /H/, etc.

The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is bypassed the 5th transmit

data bit is equivalent to TX_ER.

Note that encoding can be bypassed only when the MAC interface is configured to operate in MII mode.

FIGURE 4-1:

100BASE-TX DATA PATH

MA C

Drive r

ML T -3

C onverte r

NRZ I

C onverte r

4B /5 B

En c o d e r

Ma g n e tic s

CAT -5

RJ 4 5

25M H z by

5 bits

NR Z I

ML T -3

Sc ra m b le r

a n d PISO

125 M b p s S e rial

MII

25 M H z

by 4 bits

T X _C LK

(for M II only)

E x t Re f_ CL K (fo r RM II o n ly)

10 0M

PL L

M II 2 5 M h z b y 4 b its

R M II 50 M h z by 2 bits

LAN8700 Datasheet(PDF) 14 Page - Microchip Technology

LAN8700 Datasheet(HTML) 14 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL