LAN8700 datasheet(18/74 Pages) MICROCHIP

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LAN8700/LAN8700i

DS00002260A-page 18

 2007-2016 Microchip Technology Inc.

4.3.8

RECEIVER ERRORS

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0

through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RX_ER signal is asserted and arbitrary

data is driven onto the RXD[3:0] lines. Should an error be detected during the time that the /J/K/ delimiter is being

decoded (bad SSD error), RX_ER is asserted true and the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the

Valid Data signal is not yet asserted when the bad SSD error occurs.

4.3.9

100M RECEIVE DATA ACROSS THE MII/RMII INTERFACE

In MII mode, the 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the controller at a rate

of 25MHz. The controller samples the data on the rising edge of RX_CLK. To ensure that the setup and hold require-

ments are met, the nibbles are clocked out of the PHY on the falling edge of RX_CLK. RX_CLK is the 25MHz output

clock for the MII bus. It is recovered from the received data to clock the RXD bus. If there is no received signal, it is

derived from the system reference clock (CLKIN).

When tracking the received data, RX_CLK has a maximum jitter of 0.8ns (provided that the jitter of the input clock,

CLKIN, is below 100ps).

In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate

of 50MHz. The controller samples the data on the rising edge of CLKIN/XTAL1 (REF_CLK). To ensure that the setup

and hold requirements are met, the nibbles are clocked out of the PHY on the falling edge of CLKIN/XTAL1 (REF_CLK).

4.4

10Base-T Transmit

Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives 4-bit nibbles from the

MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded

and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

• MII (digital)

• TX 10M (digital)

• 10M Transmitter (analog)

• 10M PLL (analog)

4.4.1

10M TRANSMIT DATA ACROSS THE MII/RMII INTERFACE

The MAC controller drives the transmit data onto the TXD BUS. For MII, when the controller has driven TX_EN high to

indicate valid data, the data is latched by the MII block on the rising edge of TX_CLK. The data is in the form of 4-bit

wide 2.5MHz data.

In order to comply with legacy 10Base-T MAC/Controllers, in Half-duplex mode the PHY loops back the transmitted

data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted during this

time. The PHY also supports the SQE (Heartbeat) signal. See Section 5.4.2, "Collision Detect," on page 42, for more

details.

FIGURE 4-3:

RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS

data

RXD

RX_DV

RX_CLK

data

CLEAR-TEXT

Idle

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