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LAN8700 Datasheet(PDF) 10 Page - Microchip Technology

Part # LAN8700
Description  짹15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR짰 Technology in a Small Footprint
PDF  74 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN8700 Datasheet(HTML) 10 Page - Microchip Technology

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LAN8700/LAN8700i
DS00002260A-page 10
2007-2016 Microchip Technology Inc.
RX_CLK/
REGOFF
IOPD
Receive Clock: In MII mode, this pin is the receive clock output.
25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode.
Note:
This signal is not used in RMII Mode.
Regulator Off: This pin pulled up to configure the internal 1.8V
regulator off. As described in Section 4.9, this pin is sampled
during the power-on sequence to determine if the internal
regulator should turn on. When the regulator is disabled, external
1.8V must be supplied to VDD_CORE, and the voltage at VDD33
must be at least 2.64V before voltage is applied to VDD_CORE.
COL/
RMII/
CRS_DV
IOPD
MII Mode Collision Detect: Asserted to indicate detection of
collision condition.
RMII – MII/RMII mode selection is latched on the rising edge of
the internal reset (nreset) based on the following strapping:
• Float this pin for MII mode or pull-high with an external resistor
to VDDIO (see Table 4-3, “Boot Strapping Configuration Resis-
tors,” on page 25) to set the device in RMII mode.
• See Section 4.6.3, "MII vs. RMII Configuration," on page 21 for
more details.
RMII Mode CRS_DV (Carrier Sense/Receive Data Valid)
Asserted to indicate when the receive medium is non-idle. When
a 10BT packet is received, CRS_DV is asserted, but RXD[1:0] is
held low until the SFD byte (10101011) is received. In 10BT, half-
duplex mode, transmitted data is not looped back onto the receive
data pins, per the RMII standard.
CRS/
PHYAD4
IOPU
Carrier Sense: Indicates detection of carrier.
Note:
This signal is mux’d with PHYAD4
TABLE 3-2:
LED SIGNALS
Signal Name
Type
Description
SPEED100/
PHYAD0
IOPU
LED1 – SPEED100 indication. Active indicates that the selected
speed is 100Mbps. Inactive indicates that the selected speed is
10Mbps.
Note:
This signal is mux’d with PHYAD0
LINK/
PHYAD1
IOPU
LED2 – LINK ON indication. Active indicates that the Link
(100Base-TX or 10Base-T) is on.
Note:
This signal is mux’d with PHYAD1
ACTIVITY/
PHYAD2
IOPU
LED3 – ACTIVITY indication. Active indicates that there is Carrier
sense (CRS) from the active PMD.
Note:
This signal is mux’d with PHYAD2
FDUPLEX/
PHYAD3
IOPU
LED4 – DUPLEX indication. Active indicates that the PHY is in
full-duplex mode.
Note:
This signal is mux’d with PHYAD3
TABLE 3-3:
MANAGEMENT SIGNALS
Signal Name
Type
Description
MDIO
IOPD
Management Data Input/OUTPUT: Serial management data
input/output.
MDC
IPD
Management Clock: Serial management clock.
TABLE 3-1:
MII SIGNALS (CONTINUED)
Signal Name
Type
Description



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