LAN9250 datasheet(205/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 205

LAN9250

11.15.11 HOST MAC WAKE-UP FRAME FILTER REGISTER (HMAC_WUFF)

This write-only register is used to configure the wake-up frame filter. Refer to Section 11.6.3, "Wake-up Frame Detec-

tion," on page 145 for additional information.

Offset:

0Bh

Size:

32 bits

Bits

Description

Type

Default

31:0

Wake-Up Frame Filter (WFF)

The Wake-up frame filter is configured through this register using an indexing

mechanism. After power-on reset, digital reset, or Host MAC reset, the Host

MAC loads the first value written to this location to the first DWORD in the

Wake-up frame filter (filter 0 byte mask 0). The second value written to this

location is loaded to the second DWORD in the wake-up frame filter (filter 0

byte mask 1) and so on. Once all 40 DWORDs have been written, the inter-

nal pointer will once again point to the first entry and the filter entries can be

modified in the same manner. Similarly, 40 DWORDs can be read sequen-

tially to obtain the values stored in the WFF. Please refer to Section 11.6.3,

"Wake-up Frame Detection," on page 145 for further information.

Note:

This register should be read and written using 40 consecutive

DWORD operations. Failure to read or write the entire contents of

the WFF may cause the internal read/write pointers to be left in a

position other than pointing to the first entry. A mechanism for

resetting the internal pointers to the beginning of the WFF is

available via the WFF Pointer Reset (WFF_PTR_RST) bit of the

Host MAC Wake-up Control and Status Register (HMAC_WUCSR).

This mechanism enables the application program to re-synchronize

with the internal WFF pointers if it has not previously read/written

the complete contents of the WFF.

R/W

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