LAN9250 datasheet(321/421 Pages) MICROCHIP

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DS00001913A-page 321

LAN9250

14.8.2

1588 GENERAL CONFIGURATION REGISTER (1588_GENERAL_CONFIG)

Offset:

104h

Size:

32 bits

Bank:

Bits

Description

Type

Default

31:19

RESERVED

18:17

RESERVED

Time-Stamp Unit Enable (TSU_ENABLE)

This bit enables the receive and transmit functions of the time-stamp unit.

The 1588 Enable (1588_ENABLE) bit in 1588 Command and Control Regis-

ter (1588_CMD_CTL) bit must also be set.

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

GPIO 1588 Timer Interrupt B Clear Enable

(GPIO_1588_TIMER_INT_B_CLEAR_EN)

This bit enables the selected GPIO to clear the 1588_TIMER_INT_B bit of

the 1588 Interrupt Status Register (1588_INT_STS).

The GPIO input is selected using the GPIO 1588 Timer Interrupt B Clear

Select (GPIO_1588_TIMER_INT_B_CLEAR_SEL[2:0]) bits in this register.

The polarity of the GPIO input is determined by GPIO Interrupt/1588 Polarity

2-0 (GPIO_POL[2:0]) in the General Purpose I/O Configuration Register

(GPIO_CFG).

Note:

The GPIO must be configured as an input for this function to

operate. For the clear function, GPIO inputs are edge sensitive and

must be active for greater than 40 ns to be recognized.

R/W

14:12

GPIO 1588 Timer Interrupt B Clear Select

(GPIO_1588_TIMER_INT_B_CLEAR_SEL[2:0])

These bits determine which GPIO is used to clear the 1588 Timer Interrupt B

(1588_TIMER_INT_B) bit of the 1588 Interrupt Status Register

(1588_INT_STS).

Note:

The IEEE 1588 Unit supports 3 GPIO signals.

R/W

000b

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