LAN9250 datasheet(351/421 Pages) MICROCHIP

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DS00001913A-page 351

LAN9250

14.8.25

1588 PORT RX FILTER CONFIGURATION REGISTER (1588_RX_FILTER_CONFIG)

This register is used to configure PTP message filtering.

Note:

Port and GPIO registers share a common address space. Port registers are selected by the Bank Select

(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL).

Offset:

168h

Size:

32 bits

Bank:

Bits

Description

Type

Default

31:19

RESERVED

RX PTP Alternate Master Filter Enable

(RX_PTP_ALT_MASTER_FLTR_EN)

This bit enables message filtering based on the alternateMasterFlag flagField

bit.

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

RX PTP Domain Filter Enable (RX_PTP_DOMAIN_FLTR_EN)

This bit enables message filtering based on the PTP domain.

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

RX PTP Version Filter Enable (RX_PTP_VERSION_FLTR_EN)

This bit enables message filtering based on the PTP version.

Note:

The host S/W must not change this bit while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

15:0

RX PTP Message Type Filter Enable (RX_PTP_MSG_FLTR_EN[15:0])

These bits enable individual message filtering. Bit 0 of this field corresponds

to a message type value of 0 (Sync), bit 1 to message type value 1

(Delay_Req), etc.

Typically Delay_Req and Delay_Resp messages are filtered for peer-to-peer

transparent clocks.

R/W

0000h

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