LAN9250 datasheet(395/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 395

LAN9250

17.1.3

HARDWARE CONFIGURATION REGISTER (HW_CFG)

This register allows the configuration of various hardware features including TX/RX FIFO sizes and Host MAC transmit

threshold properties. A detailed explanation of the allowable settings for FIFO memory allocation can be found in Sec-

tion 11.10.3, "FIFO Memory Allocation Configuration," on page 157.

Note:

This register can be read while the device is in the reset or not ready / power savings states without leaving

the host interface in an intermediate state. If the host interface is in a reset state, returned data may be

invalid.

Note:

It is not necessary to read all fours BYTEs of this register. DWORD access rules do not apply to this register.

Offset:

074h

Size:

32 bits

Bits

Description

Type

Default

31:28

RESERVED

Device Ready (READY)

When set, this bit indicates that the device is ready to be accessed. Upon

power-up, RST# reset, return from power savings states, Host MAC module

level reset or digital reset, the host processor may interrogate this field as an

indication that the device has stabilized and is fully active.

This rising edge of this bit will assert the Device Ready (READY) bit in the

Interrupt Status Register (INT_STS) and can cause an interrupt if enabled.

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and

RESET_CTL registers, read access to any internal resources is

forbidden while the READY bit is cleared. Writes to any address

are invalid until this bit is set.

Note:

This bit is identical to bit 0 of the Power Management Control

RESERVED

AMDIX_EN Strap State

This bit reflects the state of the auto_mdix_strap_1 strap that connects to the

PHY. The strap value is loaded with the level of the auto_mdix_strap_1

during reset and can be re-written by the EEPROM Loader. The strap value

can be overridden by bit 15 and 13 of the PHY Special Control/Status Indica-

tion Register (PHY_SPECIAL_CONTROL_STAT_IND).

Note 2

24:22

RESERVED

RESERVED - This bit must be written with 0b for proper operation.

R/W

Must Be One (MBO).

This bit must be set to ‘1’ for normal device operation.

R/W

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