LAN9250 datasheet(391/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 391

LAN9250

16.4.4

GENERAL PURPOSE I/O INTERRUPT STATUS AND ENABLE REGISTER

(GPIO_INT_STS_EN)

This read/write register contains the GPIO interrupt status bits.

Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are

cascaded into the GPIO Interrupt Event (GPIO) bit of the Interrupt Status Register (INT_STS). Writing a 1 to any of the

interrupt enable bits will enable the corresponding interrupt as a source. Status bits will still reflect the status of the inter-

rupt source regardless of whether the source is enabled as an interrupt in this register. The GPIO Interrupt Event Enable

(GPIO_EN) bit of the Interrupt Enable Register (INT_EN) must also be set in order for an actual system level interrupt

to occur. Refer to Section 8.0, "System Interrupts," on page 62 for additional information.

Offset:

1E8h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:19

RESERVED

18:16

GPIO Interrupt Enable[2:0] (GPIO[2:0]_INT_EN)

When set, these bits enable the corresponding GPIO interrupt.

Note:

The GPIO interrupts must also be enabled via the GPIO Interrupt

Event Enable (GPIO_EN) bit of the Interrupt Enable Register

(INT_EN) in order to cause the interrupt pin (IRQ) to be asserted.

R/W

000b

15:3

RESERVED

2:0

GPIO Interrupt[2:0] (GPIO[2:0]_INT)

These signals reflect the interrupt status as generated by the GPIOs. These

interrupts are configured through the General Purpose I/O Configuration

Note:

As GPIO interrupts, GPIO inputs are level sensitive and must be

active greater than 40 ns to be recognized as interrupt inputs.

R/WC

000b

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