LAN9250 datasheet(388/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 388

 2015 Microchip Technology Inc.

16.4.2

GENERAL PURPOSE I/O CONFIGURATION REGISTER (GPIO_CFG)

This read/write register configures the GPIO input and output pins. The polarity of the GPIO pins is configured here as

well as the IEEE 1588 timestamping and clock compare event output properties. Refer to Section 14.5, "1588 GPIOs,"

on page 314 for additional 1588 information.

Offset:

1E0h

Size:

32 bits

Bits

Description

Type

Default

31:27

RESERVED

26:24

1588 GPIO Channel Select 2-0 (GPIO_CH_SEL[2:0])

These bits select the 1588 channel to be output on the corresponding

GPIO[2:0]. Refer to Section 14.5, "1588 GPIOs," on page 314 for additional

information.

0: Sets 1588 channel A as the output for the corresponding GPIO pin

1: Sets 1588 channel B as the output for the corresponding GPIO pin

R/W

000b

23:19

RESERVED

18:16

GPIO Interrupt/1588 Polarity 2-0 (GPIO_POL[2:0])

These bits set the interrupt input polarity and 1588 clock event output polarity

of the 3 GPIO pins. The configured level (high/low) will set the corresponding

GPIO_INT bit in the General Purpose I/O Interrupt Status and Enable Regis-

ter (GPIO_INT_STS_EN). 1588 clock events will be output active at the con-

figured level (high/low).

These bits also determine the polarity of the GPIO 1588 Timer Interrupt Clear

inputs. Refer to Section 14.5, "1588 GPIOs," on page 314 for additional infor-

mation.

0: Sets low logic level trigger on corresponding GPIO pin

1: Sets high logic level trigger on corresponding GPIO pin

R/W

000b

15:11

RESERVED

10:8

1588 GPIO Output Enable 2-0 (1588_GPIO_OE[2:0])

These bits configure the 3 GPIO pins to output 1588 clock compare events.

0: Disables the output of 1588 clock compare events

1: Enables the output of 1588 clock compare events

Note:

These bits override the direction bits in the General Purpose I/O

Data & Direction Register (GPIO_DATA_DIR) register. However,

the GPIO Buffer Type 2-0 (GPIOBUF[2:0]) in the General Purpose

I/O Configuration Register (GPIO_CFG) is not overridden.

R/W

000b

7:3

RESERVED

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