LAN9250 datasheet(384/421 Pages) MICROCHIP

384 / 421 page

LAN9250

DS00001913A-page 384

 2015 Microchip Technology Inc.

16.0

GPIO/LED CONTROLLER

16.1

Functional Overview

The GPIO/LED Controller provides 3 configurable general purpose input/output pins, GPIO[2:0]. These pins can be indi-

vidually configured to function as inputs, push-pull outputs or open drain outputs and each is capable of interrupt gen-

eration with configurable polarity. Alternatively, all 3 GPIO pins can be configured as LED outputs, enabling these pins

to drive Ethernet status LEDs for external indication of various attributes of the port. All GPIOs also provide extended

1588 functionality. Refer to Section 14.5, "1588 GPIOs," on page 314 for additional details.

GPIO and LED functionality is configured via the GPIO/LED System Control and Status Registers (CSRs). These reg-

isters are defined in Section 16.4, "GPIO/LED Registers," on page 386.

16.2

GPIO Operation

The GPIO controller is comprised of 3 programmable input/output pins. These pins are individually configurable via the

GPIO CSRs. On application of a chip-level reset:

• All GPIOs are set as inputs (GPIO Direction 2-0 (GPIODIR[2:0]) cleared in General Purpose I/O Data & Direction

• All GPIO interrupts are disabled (GPIO Interrupt Enable[2:0] (GPIO[2:0]_INT_EN) cleared in General Purpose I/O

Interrupt Status and Enable Register (GPIO_INT_STS_EN)

• All GPIO interrupts are configured to low logic level triggering (GPIO Interrupt/1588 Polarity 2-0 (GPIO_POL[2:0])

cleared in General Purpose I/O Configuration Register (GPIO_CFG))

Note:

GPIO[2:0] may be configured as LED outputs by default, dependent on the LED_en_strap[2:0] configuration

straps. Refer to Section 16.3, "LED Operation" for additional information.

The direction and buffer type of all GPIOs are configured via the General Purpose I/O Configuration Register (GPI-

O_CFG) and General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). The direction of each GPIO, input or

output, should be configured first via its respective GPIO Direction 2-0 (GPIODIR[2:0]) bit in the General Purpose I/O

Data & Direction Register (GPIO_DATA_DIR). When configured as an output, the output buffer type for each GPIO is

selected by the GPIO Buffer Type 2-0 (GPIOBUF[2:0]) bits in the General Purpose I/O Configuration Register (GPI-

O_CFG). Push/pull and open-drain output buffers are supported for each GPIO. When functioning as an open-drain

driver, the GPIO output pin is driven low when the corresponding GPIO Data 2-0 (GPIOD[2:0]) bit in the General Pur-

pose I/O Data & Direction Register (GPIO_DATA_DIR) is cleared to 0 and is not driven when set to 1.

When a GPIO is enabled as a push/pull output, the value output to the GPIO pin is set via the corresponding GPIO Data

2-0 (GPIOD[2:0]) bit in the General Purpose I/O Data & Direction Register (GPIO_DATA_DIR). For GPIOs configured

as inputs, the corresponding GPIO Data 2-0 (GPIOD[2:0]) bit reflects the current state of the GPIO input.

In GPIO mode, the input buffers are disabled when the pin is set to an output and the pull-ups are normally enabled.

Note:

Upon reset, GPIOs that were outputs may generate an active interrupt status as the system settles - typically

when a low GPIO pin slowly rises due to the internal pull-up. The interrupt status bits within the General

Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) should be cleared as part of the

device initialization software routine.

16.2.1

GPIO INTERRUPTS

Each GPIO provides the ability to trigger a unique GPIO interrupt in the General Purpose I/O Interrupt Status and Enable

rent status of the corresponding interrupt and each interrupt is enabled by setting the corresponding GPIO Interrupt

Enable[2:0] (GPIO[2:0]_INT_EN) bit. The GPIO/LED Controller aggregates the enabled interrupt values into an internal

signal that is sent to the System Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) GPIO

Interrupt Event (GPIO) bit. For more information on interrupts, refer to Section 8.0, "System Interrupts," on page 62.

As interrupts, GPIO inputs are level sensitive and must be active for greater than 40 ns to be recognized.

16.2.1.1

GPIO Interrupt Polarity

The interrupt polarity can be set for each individual GPIO via the GPIO Interrupt/1588 Polarity 2-0 (GPIO_POL[2:0]) bits

in the General Purpose I/O Configuration Register (GPIO_CFG). When set, a high logic level on the GPIO pin will set

the corresponding interrupt bit in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN).

When cleared, a low logic level on the GPIO pin will set the corresponding interrupt bit.

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