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LAN9250 Datasheet(PDF) 409 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 409 Page - Microchip Technology |
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409 / 421 page ![]() 2015 Microchip Technology Inc. DS00001913A-page 409 LAN9250 19.6.2 POWER SEQUENCING TIMING These diagrams illustrates the device power sequencing requirements. The VDDIO, VDD33, VDD33TXRX1, VDD33TXRX2, VDD33BIAS and magnetics power supplies must all reach operational levels within the specified time period tpon. When operating with the internal regulators disabled, VDDCR, OSCVDD12, VDD12TX1 and VDD12TX2 are also included into this requirement. In addition, once the VDDIO power supply reaches 1.0 V, it must reach 80% of its operating voltage level (1.44 V when operating at 1.8 V, 2.0 V when operating at 2.5 V, 2.64 V when operating at 3.3 V) within an additional 15ms. This requirement can be safely ignored if using an external reset as shown in Section 19.6.3, "Reset and Configuration Strap Timing". Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period tpoff. FIGURE 19-2: POWER SEQUENCE TIMING - INTERNAL REGULATORS FIGURE 19-3: POWER SEQUENCE TIMING - EXTERNAL REGULATORS TABLE 19-10: POWER SEQUENCING TIMING VALUES Symbol Description Min Typ Max Units tpon Power supply turn on time - - 50 ms tpoff Power supply turn off time - - 500 ms VDDIO Magnetics Power tpon tpoff VDD33, VDD33BIAS, VDD33TXRX1, VDD33TXRX2 VDDIO Magnetics Power tpon tpoff VDD33, VDD33BIAS, VDD33TXRX1, VDD33TXRX2 VDDCR, OSCVDD12, VDD12TX1, VDD12TX2 |
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