DS26401 datasheet(108/309 Pages) DALLAS

108 / 309 page

DS26401 Octal T1/E1/J1 Framer

108

9.2 T1 Transmit Formatter Description and Operation

Eight fully independent DS1/E1 transmit formatters are included within the DS26401. The formatters are designed

to interface seamlessly to the line via an external LIU. Each port can be individually programmed to transmit AMI,

B8ZS, HDB3, or NRZ data. In T1 mode each formatter supports D4 (SF), ESF, and SLC-96 frame formats, and

transmits common alarms such as AIS, RAI, AIS-CI, and RAI-CI.

Each framer also has an HDLC controller which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1

Mode) or the FDL (T1 Mode) and has 64 byte FIFO buffers in both the transmit and receive paths. The user can

select any specific bits within the time slot(s) to assign to the HDLC controllers, as well as specific Sa bits (E1

Mode).

The HDLC controllers perform all the necessary overhead for generating and receiving Performance Report

Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The controllers

automatically generate and detects flags, generate and check the CRC check sum, generate and detect abort

sequences, stuff and de-stuff zeros, and byte align to the data stream. The large FIFO buffers allow a full PRM to

be received or transmitted without host intervention.

Other features contained within each framer include a BOC generator and a 16-bit loop code generator. Host

interface is simplified with status registers optimized for either interrupt driven or polled environments. In many

cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state

change. Most latched bits can be enabled to generate an external interrupt on the INT pin.

Additional details concerning the operation of the DS1 formatter are included within the register descriptions within

this section.

DS26401 Datasheet(PDF) 108 Page - Dallas Semiconductor