DS26401 datasheet(137/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

137

9.17.2 HDLC Status and Information

TLS2 provides status information for the transmit HDLC controller. When a particular event has occurred (or is

occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers are

latched and some are real time bits that are not latched. This section contains register descriptions that list which

bits are latched and which are real time. With the latched bits, when an event occurs and a bit is set to a one, it will

remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the

event has occurred again. The real time bits report the current instantaneous conditions that are occurring and the

history of these bits is not latched.

Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the

register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not affected by

writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or

she wishes to clear and a zero in the bit positions he or she does not wish to clear.

The HDLC status register, TLS2 has the ability to initiate a hardware interrupt via the INT output signal. Each of the

events in this register can be either masked or unmasked from the interrupt pin via the receive HDLC Interrupt

Mask Register (TIM2). Interrupts will force the INT signal low when the event occurs. The INT pin will be allowed to

return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.

TRTS2

Transmit Real-Time Status Register 2 (HDLC)

1B1h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

—

TEMPTY

TFULL

TLWM

TNF

Default

All bits in this register are real time.

Bit 0 / Transmit FIFO Not Full Condition (TNF).

Set when the transmit 64-byte FIFO has at least 1 byte available.

Bit 1 / Transmit FIFO Below Low Watermark Condition (TLWM).

Set when the transmit 64-byte FIFO empties

beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM).

Bit 2 / Transmit FIFO Full (TFULL).

A real-time bit that is set high when the FIFO is full.

Bit 3 / Transmit FIFO Empty (TEMPTY).

A real-time bit that is set high when the FIFO is empty.

Bits 4 to 7 / Unused

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