DS26401 datasheet(140/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

140

9.17.3 FIFO Information

The Transmit FIFO Buffer Available register indicates the number of bytes that can be written into the transmit

FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO

without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read

cycle.

TFBA

Transmit HDLC FIFO Buffer Available

1B3h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

TFBA6

TFBA5

TFBA4

TFBA3

TFBA2

TFBA1

TFBA0

Default

Bits 0 to 6 / Transmit FIFO Bytes Available (TFBAO to TFBA6).

TFBA0 is the LSB.

THF

Transmit HDLC FIFO

1B4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

THD7

THD6

THD5

THD4

THD3

THD2

THD1

THD0

Default

Bit 0 / Transmit HDLC Data Bit 0 (THD0).

LSB of a HDLC packet data byte.

Bit 1 / Transmit HDLC Data Bit 1 (THD1)

Bit 2 / Transmit HDLC Data Bit 2 (THD2)

Bit 3 / Transmit HDLC Data Bit 3 (THD3)

Bit 4 / Transmit HDLC Data Bit 4 (THD4)

Bit 5 / Transmit HDLC Data Bit 5 (THD5)

Bit 6 / Transmit HDLC Data Bit 6 (THD6)

Bit 7 / Transmit HDLC Data Bit 7 (THD7).

MSB of a HDLC packet data byte.

DS26401 Datasheet(PDF) 140 Page - Dallas Semiconductor

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