DS26401 datasheet(138/309 Pages) DALLAS

138 / 309 page

DS26401 Octal T1/E1/J1 Framer

138

TLS2

Transmit Latched Status Register 2 (HDLC)

191h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

—

TFDLE

TUDR

TMEND

TLWMS

TNFS

Default

All bits in this register are latched and can create interrupts.

Bit 0 / Transmit FIFO Not Full Set Condition (TNFS).

Set when the transmit 64–byte FIFO has at least one empty

byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.

Bit 1 / Transmit FIFO Below Low Watermark Set Condition (TLWMS).

Set when the transmit 64-byte FIFO

empties beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM) (rising edge detect of

TLWM).

Bit 2 / Transmit Message End Event (TMEND).

Set when the transmit HDLC controller has finished sending a

message.

Bit 3 / Transmit FIFO Underrun Event (TUDR).

Set when the transmit FIFO empties out without having seen the

TMEND bit set. An abort is automatically sent.

Bit 4 / Transmit FDL Register Empty (TFDLE).

Set when the TFDL register has shifted out all 8 bits. Useful if the

user wants to manually use the TFDL register to send messages, instead of using the HDLC or BOC controller

circuits.

Bits 5 to 7 / Unused

DS26401 Datasheet(PDF) 138 Page - Dallas Semiconductor