DS26401 datasheet(155/309 Pages) DALLAS

155 / 309 page

DS26401 Octal T1/E1/J1 Framer

155

10.2 E1 Receive Framer Description and Operation

Eight fully independent DS1/E1 framers are included within the DS26401. The framers are designed to interface

seamlessly to the line side via an external LIU. Each framer can be individually programmed to accept AMI, HDB3

(E1), B8ZS (T1), or NRZ data. In E1 mode each framer supports FAS, CRC-4, and CAS frame formats, and

detects/reports common alarms such as AIS, RAI, LOS, and LOF. Performance monitor counters are maintains for

each port which report bipolar/line code violations, CRC-4 errors, FAS errors, and E-bits.

Each framer has an HDLC controller which can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or

the FDL (T1 Mode) and includes 64 byte FIFO buffers in both the transmit and receive paths.

Host interface is simplified with status registers optimized for either interrupt driven or polled environments. In

many cases, status bits are reported both real-time and latched on change-of-state with separate bits for each state

change. Most latched bits can be mapped to generate an external interrupt on the INT pin.

Interface to the system backplane is simplified with flexible, 2 frame elastic-store buffers. An interleaved backplane

option is also provided that supports 4.096, 8.192, or 16.384 MHz operation.

Additional details concerning the operation of the E1 framer are included within the register descriptions within this

section.

DS26401 Datasheet(PDF) 155 Page - Dallas Semiconductor