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DS26401 Datasheet(PDF) 240 Page - Dallas Semiconductor |
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DS26401 Datasheet(HTML) 240 Page - Dallas Semiconductor |
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240 / 309 page  DS26401 Octal T1/E1/J1 Framer 240 11.16 Additional (Sa) and International (Si) Bit Operation (E1 Mode) On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align Frame bit in Transmit Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update the TAF and TNAF registers. It has 250 ms to update the data or else the old data will be retransmitted. If the TAF an TNAF registers are only being used to source the align frame and non-align frame sync patterns then the host need only write once to these registers . Data in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. There is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that via the Transmit Sa-Bit Control Register (TSaCR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or else the old data will be retransmitted. |
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