DS26401 datasheet(239/309 Pages) DALLAS

239 / 309 page

DS26401 Octal T1/E1/J1 Framer

239

11.15 Fractional E1 Support (Gapped Clock Mode)

The DS26401 can be programmed to output gapped clocks for selected channels in the receive and transmit paths

to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN–PRI applications. When the

gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled

via the transmit-gapped-clock channel-select registers (TGCCS1-TGCCS4). The transmit path is enabled for

gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as

determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the Data/Control bit in the

channel is omitted (only the seven most significant bits of the channel have clocks).

TGCCS1, TGCCS2, TGCCS3, TGCCS4

Transmit Gapped Clock Channel Select Registers

1CCh, 1CDh, 1CEh, 1CFh [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8]

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

TGCCS1

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

TGCCS2

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

TGCCS3

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

TGCCS4

Bits 0 to 7 / Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32)

0 = no clock is present on TCHCLK during this channel time

1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLK if the

elastic store is disabled, and synchronous with TSYSCLK if the elastic store is enabled.

DS26401 Datasheet(PDF) 239 Page - Dallas Semiconductor

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