DS26401 datasheet(236/309 Pages) DALLAS

236 / 309 page

DS26401 Octal T1/E1/J1 Framer

236

11.14.1 Elastic Stores Initialization

There are two elastic store initializations that may be used to improve performance in certain applications, Elastic

Store Reset and Elastic Store Align. Both of these involve the manipulation of the elastic store’s read and write

pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK,

respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align

bit is used to 'center' the read/write pointers to the extent possible.

Elastic Store Delay After Initialization

INITIALIZATION

BIT

DELAY

Receive Elastic Store Reset

RESCR.2

N bytes < Delay < 1 Frame + N bytes

Transmit Elastic Store Reset

TESCR.2

N bytes < Delay < 1 Frame + N bytes

Receive Elastic Store Align

RESCR.3

1/2 Frame < Delay < 1 1/2 Frames

Transmit Elastic Store Align

TESCR.3

1/2 Frame < Delay < 1 1/2 Frames

N = 9 for TSZS = 0

N = 2 for TSZS = 1

11.14.2 Minimum Delay Mode

Elastic store minimum delay mode may be used when the elastic store’s system clock is locked to its network clock

(i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). TESCR.1

and RESCR.1 enable the transmit and receive elastic store minimum delay modes. When enabled the elastic

stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful

primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is

used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive

elastic store is in minimum delay mode and TSYNC must be configured as an output when transmit minimum delay

mode is enabled. The RSYNC and TSYNC outputs are registered on the rising edge of RSYSCLK and TSYSCLK

respectfully. In a typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output

mode) is connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled (since

slips cannot occur). On power–up after the RSYSCLK and TSYSCLK signals have locked to their respective

network clock signals, the elastic store reset bits (TESCR.2 and RESCR.2) should be toggled from a zero to a one

to ensure proper operation.

DS26401 Datasheet(PDF) 236 Page - Dallas Semiconductor