DS26401 datasheet(235/309 Pages) DALLAS

235 / 309 page

DS26401 Octal T1/E1/J1 Framer

235

11.14 E1 Transmit Elastic Stores Operation

The DS26401 contains dual two-frame elastic stores, one for the receive direction, and one for the transmit

direction. Both elastic stores are fully independent. The transmit and receive side elastic stores can be

enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or

2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate of the other elastic store.

The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26401 is in the

T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic

store can rate convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the

differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked)

backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the elastic stores will manage the rate

difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference

between the network and the backplane. Note that TCBR4 will not be active when the transmitter is enabled with a

1.544MHz backplane.

The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the

Interleave Bus Option (IBO) which is discussed in Section 11.19.

Note that the receive elastic store status bits are contained in TLS1 with the associated interrupt bits located in

TIM1. These bits indicate a receive slip event, or when the e-store FIFO is in a ‘full’ or ‘empty’ condition. See the

The operation of the transmit elastic store is very similar to the receive side. If the transmit side elastic store is

enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a frame sync

pulse or a multiframe sync pulse to the TSSYNC input. For higher rate system clock applications, see the Interleave

Bus Option section. Controlled slips in the transmit elastic store are reported in the TLS1.5 bit and the direction of

the slip is reported in the TLS1.6 and TLS1.7 bits.

DS26401 Datasheet(PDF) 235 Page - Dallas Semiconductor