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Data Sheet

AD9625

Rev. C | Page 33 of 72

DIGITAL DOWNCONVERTERS (DDC)

SYNTHESIZER

NCO

12-BIT ADC

@ 2.0GSPS

DECIMATION

BY 8

GAIN SELECT:

0dB, 6dB, 12dB, 18dB

MODE SELECT:

96MHz OR 192MHz BW

MIXER

8 × 12-BIT

@ 250MHz

DECIMATION

BY 8

DECIMATION

BY 2

8 × 13-BIT

@ 250MHz

8 × 12-BIT

@ 250MHz

8 × 13-BIT

@ 250MHz

16-BIT @ 250MHz

16-BIT

@ 125MHz

16-BIT

@ 125MHz

I-PHASE

16-BIT @ 250MHz

Q-PHASE

TUNER SELECT:

–1.0GHz TO +1.0GHz

GAIN SELECT:

0dB, 6dB,

12dB, 18dB

FRAMER

Figure 82. Digital Downconverter Block Diagram Operating at 2.0 GSPS

The AD9625 architecture includes two DDCs, each designed to

extract a portion of the full digital spectrum captured by the

ADC. Each tuner consists of an independent frequency synthesizer

and quadrature mixer; a chain of low-pass filters for rate conversion

follows these components. Assuming a sampling frequency of

2.500 GSPS, the frequency synthesizer (10-bit NCO) allows for

1024 discrete tuning frequencies, ranging from −1.2499 GHz to

+1.2500 GHz, in steps of 2500/1024 = 2.44 MHz. The low-pass

filters allow for two modes of decimation.



A high bandwidth mode, 240 MHz wide (from −120 MHz

to +120 MHz), sampled at 2.5 GHz/8 = 312.5 MHz for the

I and Q branches separately. The 16-bit samples from the I

and Q branches are transmitted through a dedicated

JESD204B interface.



A low bandwidth mode, 120 MHz wide (from −60 MHz to

+60 MHz), sampled at 2.5 GHz/16 = 156.25 MHz for the I

and Q branches separately. The 16-bit samples from the I

and Q branches are transmitted through a dedicated

JESD204B interface.

By design, all of the blocks operate at a single clock frequency of

2.5 GHz/8 = 312.5 MHz.

Each filter stage includes a gain control block that is programmable

by the user. The gain varies from 0 dB to 18 dB, in steps of 6 dB,

and the gain is applied before final scaling and rounding. The

gain control feature may be useful in cases where the tuner

filters out a strong out-of-band interferer, leaving a weak

in-band signal.

FREQUENCY SYNTHESIZER AND MIXER

For a sampling rate of 2.500 GHz, the synthesizer (10-bit

NCO) outputs one of 1024 possible complex frequencies from

−1.249 GHz to +1.250 GHz. The synthesizer employs the direct

digital synthesis technique, using look-up sine tables and a

phase accumulator. The user specifies the tuner frequency by

writing to a 10-bit phase increment register.

NUMERICALLY CONTROLLED OSCILLATOR

Each DDC has a 10-bit oscillator that is synthesized and mixed

with the ADC output data. The 10-bit phase can be tuned for

each DDC based on the value used in its NCO registers. The

phase for DDC0 is located with Register 0x132 and Register 0x131.

The phase for DDC1 is located with Register 0x13A and

(decimal(Register 0x132[1:0]; Register 0x131[7:0]) × fS)/1024. The

NCO output frequency for DDC1 = (decimal(Register 0x13A[1:0];

HIGH BANDWIDTH DECIMATOR

The first filter stage is designed for a rate reduction factor of 8,

yielding a sample rate of 2.500 GHz/8 = 312.5 MHz. To achieve

a combination of low complexity and low clock rate, the DDC

employs a decimate-by-8 polyphase fuse filter that receives

eight 13-bit samples from the mixer block at every clock cycle.

The block design provides user specified gain control, from 0 dB to

18 dB in steps of 6 dB. The gain is applied before final scaling

and rounding to 16 bits.

AD9625 Datasheet(PDF) 35 Page - Analog Devices

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