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AD9625

Data Sheet

Rev. C | Page 28 of 72

THEORY OF OPERATION

ADC ARCHITECTURE

The AD9625 is a pipelined ADC. The pipelined architecture

permits the first stage to operate on a new input sample and the

remaining stages to operate on the preceding samples. Sampling

occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The residue amplifier magnifies the difference between

the reconstructed DAC output and the flash input for the next

stage in the pipeline. One bit of redundancy is used in each stage

to facilitate digital correction of flash errors. The last stage simply

consists of a flash ADC.

The input stage contains a differential sampling circuit that can

be ac- or dc-coupled in differential or single-ended modes. The

output staging block aligns the data, corrects errors, and passes

the data to the output buffers. The output buffers are powered

from a separate supply, allowing adjustment of the output drive

current.

Synchronization capability is provided to allow synchronized

timing between multiple devices.

FAST DETECT

The fast detect block within the AD9625 generates a fast

detection bit (FD), which, when used with variable gain

amplifier front-end blocks, reduces the gain and prevents the

ADC input signal levels from exceeding the converter range.

Figure 71 shows the rapidity by which the detection bit is

programmable using an upper threshold, lower threshold,

and dwell time.

The FD bit is set when the absolute value of the input signal

exceeds the programmable upper threshold level. The FD bit

clears only when the absolute value of the input signal drops

below the lower threshold level for greater than the programmable

dwell time, thereby providing hysteresis and preventing the FD

bit from excessive toggling.

GAIN THRESHOLD OPERATION

For best performance, the AD9625 needs an input signal to

perform internal calibration. This signal needs to exceed a set

threshold that is established through register settings. The

threshold prohibits background calibration updates for small

signal amplitudes. The threshold for gain calibration is enabled

by default.

Threshold Operation

The absolute value of every sample is accumulated to produce

an average voltage estimate.

When the calibration has run for its predetermined number of

samples, the voltage estimate is compared to the data set threshold.

If the voltage estimate is greater than the threshold, the cali-

bration coefficients update; otherwise, no update occurs.

Threshold Format

The threshold registers are all 16-bit registers loaded via the SPI

one byte at a time. The threshold values range from 0 to 16,384,

corresponding to a voltage range of 0.0 V to 1.2 V (full scale).

The calibration threshold range is 0 to 16,384 (0x00 to 0x4000,

hexadecimal) and represents the average magnitude of the

input. For example, to set the threshold so that a −6 dBFS input

sine wave sits precisely at the threshold requires a threshold

setting of

16,384 ×





≥ 5228

UPPER THRESHOLD

LOWER THRESHOLD

DWELL TIME

TIMER RESET BY

RISE ABOVE LT

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE LT

DWELL TIME

Figure 71. Fast Detection Bit

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