AD9625 datasheet(49/74 Pages) AD

49 / 74 page

Data Sheet

AD9625

Rev. C | Page 47 of 72

In the case where the encode clock used for the AD9625 is

sufficiently fast (>1.75 GSPS), the guardband delays for the

earliest setup and latest hold condition starts to overlap in time

due to the fast clock period. This case occurs when the encode

clock period is smaller than 16× the nominal delay guardband

window of 35 ps or (1/fS < 16 × 35 ps). The earliest setup guard-

band delays from clock N can overlap with the latest guardband

delays from CLK±[N + 1]. When this is the case, a SYSREF±

edge located in one of these overlapped guardband delays

triggers an IRQ event for both the setup and hold detection.

While it is possible to make use of this information, it is

suggested to limit the number of valid settings to no more

than 5 (100b) and below when sampling above 1.75 GSPS to

avoid this situation.

CLK+

SYSREF–

SYSREF+

CLK–

HOLD AND

GUARDBAND TIME [N]

SETUP AND

GUARDBAND TIME [N + 1]

HOLD GUARDBAND

[N] IRQ DELAYS

SETUP GUARDBAND

[N +1] IRQ DELAYS

CLK±[N]

CLK±[N + 1]

Figure 100. SYSREF± Edge Falls Within Both the Latest Hold Time

Guardbanded of CLK±[N] and the Earliest Setup Time Guardband of

CLK±[N + 1] and Triggers an IRQ Error

Table 23. IRQ Outcomes for All Setup or Hold Guardband

Settings Using the Case in Figure 100

Setting/IRQ

Setup

Hold

000

001

010

011

100

101

110

111

As a secondary use, the SYSREF± edge detector can also alert

the system about phase shift drift between SYSREF± and CLK

due to temperature or supply changes. For example, a conservative

guardband setting could be used, such that an IRQ status of 0

would be seen in ideal conditions. If timing drifts were significant

enough to trigger the IRQ, the system would take action to

adjust the skew of the SYSREF± to CLK accordingly to reestablish

an IRQ of 0.

CLK+

SYSREF–

SYSREF+

CLK–

SETUP AND

GUARDBAND TIME

HOLD AND

GUARDBAND TIME

SETUP GUARDBAND

IRQ DELAYS

HOLD GUARDBAND

IRQ DELAYS

Figure 101. SYSREF± Edge Changes Phase Relative to the Encode Clock,

Which can be Detected When the Edge Crosses Through the Guardband

Setup Time

Table 24. IRQ Outcomes for all Setup or Hold Guardband

Settings Using the Case in Figure 101

Setting/IRQ

Setup

Hold

Setting/IRQ

Setup

Hold

000

001

010

011

100

101

110

111

Using Rising/Falling Edges of the CLK to Latch SYSREF±

The SYSREF± signal can be latched on either the rising or

falling edge of the encode clock, based on the value of register

0x03A[3] = 0 (latch on rising edge) or 0x03A[3] = 1 (latch on

falling edge). This does not impact the analog input, which is

always sampled on the rising edge of the encode clock. For

sampling SYSREF±, the falling edge encode capture of CLK±[N]

precedes the rising edge encode capture of CLK±[N], both

corresponding to the same analog sample.

AD9625 Datasheet(PDF) 49 Page - Analog Devices

AD9625 Datasheet(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL