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AD9625 Datasheet(PDF) 44 Page - Analog Devices |
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AD9625 Datasheet(HTML) 44 Page - Analog Devices |
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44 / 74 page ![]() AD9625 Data Sheet Rev. C | Page 42 of 72 Quick Configuration Value Description Lanes (L) Logical Lane 0 Logical Lane 1 Logical Lane 2 Logical Lane 3 Logical Lane 4 Logical Lane 5 Logical Lane 6 Logical Lane 7 0xE4 Dual DDC, mixed BW 4 I0[N] Q0[N] I1[N] Q1[N] Off Off Off Off 0xD1 Dual DDC, low BW 1 I0[N], Q0[N], I1[N], Q1[N] Off Off Off Off Off Off Off 0xD2 Dual DDC, low BW 2 I0[N], Q0[N] I1[N], Q1[N] Off Off Off Off Off Off Table 18. Typical Current Consumption per ADC Mode (Unused Output Lanes are Powered Down) Quick Configuration Value Mode Lanes (L) Sample Rate (MSPS) Typical Current Consumption (A) IAVDD1 IAVDD2 IDRVDD1 IDRVDD2 IDVDD1 IDVDD2 Total Power (W) 0x02 Generic, two lane 2 650 0.7 0.3 0.2 0.0 0.1 0.0 2.1 0x04 Generic, four lane 4 1300 0.9 0.3 0.3 0.0 0.2 0.0 2.6 0x06 Generic, six lane 6 2600 1.2 0.4 0.4 0.0 0.4 0.0 3.4 0x08 Generic, eight lane 8 2600 1.2 0.4 0.5 0.0 0.4 0.0 3.9 0x42 fS × 8 2 813 0.7 0.4 0.2 0.0 0.2 0.0 2.3 0x44 fS × 4 4 1625 1.0 0.4 0.3 0.0 0.3 0.0 3.0 0x48 fS × 2 8 2600 1.2 0.4 0.5 0.0 0.4 0.0 3.8 0x81 Single DDC high BW, one lane 1 1300 0.9 0.4 0.1 0.0 0.3 0.0 2.7 0x82 Single DDC high BW, two lane 2 2600 1.2 0.4 0.2 0.0 0.6 0.0 3.6 0x91 Single DDC low BW, one lane 1 2600 1.2 0.4 0.1 0.0 0.6 0.0 3.5 0xC1 Dual DDC high BW, one lane 1 650 0.7 0.4 0.1 0.0 0.2 0.0 2.3 0xC2 Dual DDC high BW, two lane 2 1300 0.9 0.4 0.2 0.0 0.5 0.0 2.9 0xC4 Dual DDC high BW, four lane 4 2600 1.2 0.4 0.3 0.0 0.8 0.0 4.0 0xE1 Dual DDC mixed BW, one lane 1 650 0.7 0.4 0.1 0.0 0.2 0.0 2.3 0xE2 Dual DDC mixed BW, two lane 2 1300 0.9 0.4 0.2 0.0 0.5 0.0 2.9 0xE4 Dual DDC mixed BW, four lane 4 2600 1.2 0.4 0.3 0.0 0.8 0.0 4.0 0xD1 Dual DDC low BW, one lane 1 1300 0.9 0.4 0.1 0.0 0.4 0.0 2.8 0xD2 Dual DDC low BW, two lane 2 2600 1.2 0.4 0.2 0.1 0.8 0.0 4.0 |
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