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AD9625

Data Sheet

Rev. C | Page 32 of 72

DC COUPLING

The AD9625 can operate using a dc-coupled input configura-

tion. The differential analog common-mode input signal would

need to be referenced to the VCM output of the AD9625.

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD9625 sample clock

inputs (CLK+ and CLK−) with a differential signal. This

signal is typically ac-coupled to the CLK+ and CLK− pins via a

transformer or capacitors. These pins are biased internally and

require no additional biasing.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) can be calculated by

SNR = 20 × log 10(1/(2 × π × fA × tJ))

In this equation, the rms aperture jitter represents the root-

mean-square of all jitter sources, including the clock input,

analog input signal, and ADC aperture jitter specifications. IF

undersampling applications are particularly sensitive to jitter

(see Figure 81).

130

120

110

100

1000

10000

ANALOG INPUT FREQUENCY (MHz)

12.5

100

200

400

800

Figure 81. Ideal SNR vs. Analog Input Frequency and Jitter

In cases where aperture jitter may affect the dynamic range of

the AD9625, treat the clock input as an analog signal. To avoid

modulating the clock signal with digital noise, separate power

supplies for clock drivers from the ADC output driver supplies.

Low jitter, crystal-controlled oscillators make the best clock

sources. If the clock is generated from another type of source (by

gating, dividing, or other methods), it should be retimed by the

original clock at the last step. Refer to the AN-501 Application

Note and the AN-756 Application Note for more information

about jitter performance as it relates to ADCs.

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics.

AD9625 Datasheet(PDF) 34 Page - Analog Devices

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