AD9625 datasheet(9/74 Pages) AD

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Data Sheet

AD9625

Rev. C | Page 7 of 72

SWITCHING SPECIFICATIONS

AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal

reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Temperature1

Min

Typ

Max

Unit

CLOCK (CLK)

Maximum Clock Rate

Full

2600

MSPS

Minimum Clock Rate

Full

3302

MSPS

Clock Pulse Width High

Full

50 ± 5

% duty cycle

Clock Pulse Width Low

Full

50 ± 5

% duty cycle

SYSREF (SYSREF±)3

Setup Time (tSU_SR)

25°C

+200

Hold Time (tH_SR)

25°C

−100

FAST DETECT OUTPUT (FD)

Latency

Full

Clock cycles

OUTPUT PARAMETERS (SERDOUT[x]±)

Rise Time

25°C

Fall Time

25°C

Pipeline Latency

Eight lane mode

25°C

226

Clock cycles

SYNCB± Falling Edge to First K.28 Characters

25°C

Multiframes

CGS Phase K.28 Characters Duration

25°C

Multiframes

Differential Termination Resistance

25°C

100

APERTURE

Delay

Full

200

Uncertainty (Jitter)

Full

fS rms

Out-of-Range Recovery Time

Full

Clock cycles

1 Full temperature range is −40°C to +85°C measured at the case (TC).

2 Must use a two-lane, generic output lane configuration for minimum sample rate. For more information, see the lane table in the JESD204B specification document.

3 SYSREF± setup and hold times are defined with respect to the rising SYSREF± edge and rising clock edge. Positive setup time leads the clock edge. Negative hold time

also leads the clock edge.

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

AD9625 Datasheet(PDF) 9 Page - Analog Devices

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