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AD9625 Datasheet(PDF) 43 Page - Analog Devices

Part # AD9625
Description  1.3 V/2.5 V Analog-to-Digital Converter
PDF  74 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9625 Datasheet(HTML) 43 Page - Analog Devices

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Data Sheet
AD9625
Rev. C | Page 41 of 72
Table 16. JESD204B Mode of Operation (M = 1, S = 4, N' = 16, Unless Otherwise Noted)
Quick
Configuration
Value
Description1
Lanes
(L)
Octets/
Frame (F)
Sample Clock Rate
Sample Clock
Multiplier
JESD204B Lane Rate
Minimum
MSPS
Maximum
MSPS
Minimum
Mbps
Maximum
Mbps
0x02
Generic
2
4
330
650
10
3300
6500
0x04
Generic
4
2
650
1300
5
3250
6500
0x06
Generic (N
' = 12)
6
1
1300
2500
2.5
3250
6250
0x08
Generic
8
1
1300
2500
2.5
3250
6250
0x42
fS × 8
2
4
406
813
8
3250
6500
0x44
fS × 4
4
2
813
1625
4
3250
6500
0x48
fS × 2
8
1
1625
2500
2
3250
5000
0x81
Single DDC, high BW
1
8
650
1300
5
3250
6500
0x82
Single DDC, high BW
2
4
1300
2500
2.5
3250
6250
0x91
Single DDC, low BW
1
8
1300
2500
2.5
3250
6250
0xC1
Dual DDC, high BW
1
8
330
650
10
3300
6500
0xC2
Dual DDC, high BW
2
4
650
1300
5
3250
6500
0xC4
Dual DDC, high BW
4
2
1300
2500
2.5
3250
6250
0xE1
Dual DDC, mixed BW
1
8
330
650
10
3300
6500
0xE2
Dual DDC, mixed BW
2
4
650
1300
5
3250
6500
0xE4
Dual DDC, mixed BW
4
2
1300
2500
2.5
3250
6250
0xD1
Dual DDC, low BW
1
8
650
1300
5
3250
6500
0xD2
Dual DDC, low BW
2
4
1300
2500
2.5
3250
6250
1 DDC means digital downconverter, BW means bandwidth, fS × x means sample rate multiplied by an integer (where x is an integer: 2, 4, 8).
Table 17. JESD204B Logical Lane Mapping
Quick
Configuration
Value
Description
Lanes
(L)
Logical
Lane 0
Logical
Lane 1
Logical
Lane 2
Logical
Lane 3
Logical
Lane 4
Logical
Lane 5
Logical
Lane 6
Logical
Lane 7
0x02
Generic
2
S[N],
S[N + 1]
S[N + 2],
S[N + 3]
Off
Off
Off
Off
Off
Off
0x04
Generic
4
S[N]
S[N + 1]
S[N + 2]
S[N + 3]
Off
Off
Off
Off
0x06
Generic
(N' = 12)
6
SMSB[N], SLSB[N], SMSB[N + 1], SLSB[N + 1], SMSB[N + 2], SLSB[N + 2], SMSB[N + 3], SLSB[N + 3]
Off
Off
0x08
Generic
8
SMSB[N]
SLSB[N]
SMSB[N + 1]
SLSB[N + 1]
SMSB[N + 2]
SLSB[N + 2]
SMSB[N + 3]
SLSB[N + 3]
0x42
fS × 8
2
See Figure 104, fS × 2 mode application layer (transmit)
0x44
fS × 4
4
See Figure 104, fS × 2 mode application layer (transmit)
0x48
fS × 2
8
SMSB[N], SLSB[N], SMSB[N + 1], SLSB[N + 1], SMSB[N + 2], SLSB[N + 2], SMSB[N + 3], SLSB[N + 3], SMSB[N + 4], SLSB[N + 4];
see Figure 104, fS × 2 mode application layer (transmit)
0x81
Single DDC,
high BW
1
I0[N],
Q0[N],
I0[N + 1],
Q0[N + 1]
Off
Off
Off
Off
Off
Off
Off
0x82
Single DDC,
high BW
2
I0[N],
Q0[N]
I0[N+1],
Q0[N+1]
Off
Off
Off
Off
Off
Off
0x91
Single DDC,
low BW
1
I0[N],
Q0[N],
I0[N + 1],
Q0[N + 1]
Off
Off
Off
Off
Off
Off
Off
0xC1
Dual DDC,
high BW
1
I0[N],
Q0[N],
I1[N],
Q1[N]
Off
Off
Off
Off
Off
Off
Off
0xC2
Dual DDC,
high BW
2
I0[N],
Q0[N]
I1[N],
Q1[N]
Off
Off
Off
Off
Off
Off
0xC4
Dual DDC,
high BW
4
I0[N]
Q0[N]
I1[N]
Q1[N]
Off
Off
Off
Off
0xE1
Dual DDC,
mixed BW
1
I0[N],
Q0[N],
I1[N],
Q1[N]
Off
Off
Off
Off
Off
Off
Off
0xE2
Dual DDC,
mixed BW
2
I0[N],
Q0[N]
I1[N],
Q1[N]
Off
Off
Off
Off
Off
Off



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