AD9625 datasheet(73/74 Pages) AD

73 / 74 page

Data Sheet

AD9625

Rev. C | Page 71 of 72

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system level design and layout of the AD9625, it

is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9625, it is recommended

that separate supplies are used: one supply for the analog output

(AVDD), and a separate supply for the digital outputs (DRVDD

and DVDD). The designer can use several different decoupling

capacitors to cover both high and low frequencies. Locate these

capacitors close to the point of entry at the PCB level and close

to the pins of the part with minimal trace length.

When using the AD9625, a single PCB ground plane is

sufficient. With proper decoupling and smart partitioning

of the PCB analog, digital, and clock sections, optimum

performance is easily achieved.

CLOCK STABILITY CONSIDERATIONS

When powered on, the AD9625 enters an initialization phase

during which an internal state machine sets up the biases and

the registers for proper operation. During the initialization

process, the AD9625 needs a stable clock. If the ADC clock

source is not present or not stable during ADC power-up, it

disrupts the state machine and causes the ADC to start up in

a less than optimum state. To correct this, an initialization

sequence must be invoked after the ADC clock is stable or any

change in the sampling clock frequency is made. By issuing a

digital reset via Register 0x00. The pseudo code sequence for a

digital reset is as follows:

#Stable Clock at the input to the AD9625

SPI_Write (0x00, 0x3C); # Reset

SPI_Write (0x080 0xFF) #SPI register transfer

SPI_Write (0x00, 0x00); # Clear Reset

SPI_Write (0x080 0xFF) #SPI register transfer

#Write further configurations

SPI PORT

When the full dynamic performance of the converter is

required, do not activate the SPI port. Because the SCLK, CSB,

and SDIO signals are typically asynchronous to the ADC clock,

noise from these signals can degrade converter performance.

If the on-board SPI bus is used for other devices, it may be

necessary to provide buffers between this bus and the AD9625

to keep these signals from transitioning at the converter input

pins during critical sampling periods.

AD9625 Datasheet(PDF) 73 Page - Analog Devices

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