AD9625 datasheet(39/74 Pages) AD

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Data Sheet

AD9625

Rev. C | Page 37 of 72

DIGITAL OUTPUTS

INTRODUCTION TO THE JESD204B INTERFACE

The AD9625 digital output complies with the JEDEC Standard

No. JESD204B, Serial Interface for Data Converters. JESD204B is

a protocol to link the AD9625 to a digital processing device

over a serial interface up to and above 6.5 Gbps link speeds. The

benefits of the JESD204B interface over LVDS include a reduction

in required board area for data interface routing, and enabling

smaller packages for converter and logic devices. The AD9625

supports one, two, four, six, or eight output lanes.

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported using special characters during

the initial establishment of the link. Additional data that is used

to maintain synchronization is embedded in the data stream

thereafter. A JESD204B receiver is required to complete the

serial link. For additional details on the JESD204B interface,

users are encouraged to refer to the JESD204B standard.

The AD9625 JESD204B transmit block maps to two digital

down converters for the outputs of the ADC over a link. A

link can be configured to use up to eight JESD204B lanes.

The JESD204B specification refers to a number of parameters

to define the link, and these parameters must match between

the JESD204B transmitter (AD9625 output) and receiver

(FPGA, ASIC, or logic device).

Table 14 describes the JESD204B interface nomenclature (the

terms, converter device and link, are used interchangeably in

the specification).

Table 14. JESD204B Interface Nomenclature

Symbol

Description

Samples transmitted per single converter per frame cycle

Number of converters per converter device (link)

Number of lanes per converter device (link)

Converter resolution

Total number of bits per sample

Number of control words per frame clock cycle per

converter device (link)

Number of control bits per conversion sample

Number of frames per multiframe

High density mode

Octets per frame

Control bit (overrange, timestamp)

Tail bit

The AD9625 adheres to the JESD204B draft specification,

which provides a high speed, serial, embedded clock interface

standard for data converters and logic devices. It is designed as

an MCDA-ML, Subclass 1 device that uses the SYSREF± input

signal for multichip synchronization and deterministic latency.

This design adheres to the following basic JESD204B link config-

uration parameters:



M = 1 (single converter, always for AD9625)



L = 1 to 8 (up to eight lanes)



S = 4 (four samples per JESD204B frame)



F = 1, 2, 4, 8 (up to 8 octets per frame)



N’ = 12, 16 (12- or 16-bit JESD204B word size)



HD = 0, 1 (high density mode, sample span multiple lanes)

FUNCTIONAL OVERVIEW

The block diagram in Figure 87 shows the flow of data through

the JESD204B hardware from the sample input to the physical

output. The processing can be divided into layers that are

derived from the OSI model widely used to describe the

abstraction layers of communications systems. These are the

transport layer, data link layer, and physical layer (serializer).

Each of these layers are described in detail in the following

sections.

Transport Layer

The transport layer handles packing the data (consisting of

samples and optional control bits) into 8-bit words that are sent

to the data link layer. The transport layer is controlled by rules

derived from the link configuration data. It packs data according to

the rules, adding tail bits to fill gaps when required.

Data Link Layer

The data link layer is responsible for the low level functions of

passing data across the link. These include optionally scrambling

the data, handling the synchronization process for characters,

frames, and lanes across the links, encoding 8-bit data-words

into 10-bit characters, and inserting appropriate control

characters into the data output. The data link layer is also

responsible for sending the initial lane alignment sequence

(ILAS), which contains the link configuration data, used by

the receiver (Rx) to verify the settings in the transport layer.

Physical Layer

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. The physical layer includes the serialization

circuits and the high speed drivers.

SAMPLE

CONSTRUCTION

FRAME

CONSTRUCTION

SCRAMBLER

ALIGNMENT

CHARACTER

GENERATION

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SERIALIZER

OUTPUT

PROCESSED

SAMPLES

FROM ADC

DATA LINK

LAYER

TRANSPORT

LAYER

PHYSICAL

LAYER

Figure 87. Data Flow

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