AD9625 datasheet(46/74 Pages) AD

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AD9625

Data Sheet

Rev. C | Page 44 of 72

LOGICAL LANE 0 (L0)

LOGICAL LANE 1 (L1)

LOGICAL LANE 2 (L2)

LOGICAL LANE 3 (L3)

LOGICAL LANE 4 (L4)

LOGICAL LANE 5 (L5)

LOGICAL LANE 6 (L6)

LOGICAL LANE 7 (L7)

REMAP

I/Q TO

CONVERTER

SAMPLES

SAMPLE [N]

SAMPLE [N + 1]

SAMPLE [N + 2]

SAMPLE [N + 3]

ADC

JESD204X

INTERFACE

(M = 1; L = 8; S = 4;

F = 1; N = 16; N' = 16;

CF = 0; SCR = 0, 1;

HD = 1;

K = SEE SPECS)

12-BIT ADC

SAMPLES [N]

THROUGH [N + 3]

Figure 94. DDC Mapping

Table 19. DDC Remap I/Q to Converter Samples

Application Mode

Sample[N]

Sample[N + 1]

Sample[N + 2]

Sample[N + 3]

Single DDC

I0[N]

Q0[N]

I0[N + 1]

Q0[N + 1]

Dual DDCs

I0[N]

Q0[N]

I1[N]

Q1[N]

Table 20. DDC Mixed Bandwidth Mode

JESD204B Frame Number

Sample[N]

Sample[N + 1]

Sample[N + 2]

Sample[N + 3]

Frame 0

I0[N]

Q0[N]

I1[N]

Q1[N]

Frame 1

I0[N + 1]

Q0[N + 1]

I1[N]

Q1[N]

Frame 2

I0[N + 2]

Q0[N + 2]

I1[N + 1]

Q1[N + 1]

Frame 3

I0[N + 3]

Q0[N + 3]

I1[N + 1]

Q1[N + 1]

CHECKSUM

The JESD204B checksum value is sent with the configuration

parameters during the initial lane alignment sequence. Disabling

the checksum is primarily for debug purposes only.

8-BIT/10-BIT ENCODER CONTROL

The 8-bit/10-bit encoder must be controlled in the following

manner:



The bypass 8-bit/10-bit encoder is controlled by

8-bit/10-bit bypassed).



The invert 10-bit encoder is controlled by Register 0x060,

Bit 1 (0 = normal; 1 = invert).



The mirror 10-bit encoder is controlled by Register 0x060,

Bit 0 (0 = normal; 1 = mirrored).

The inversion of the 10-bit values allows the user to swap the

true/complement differential pins swapped on the boards. For

details about Register 0x060, see the Memory Map Register

section.

INITIAL LANE ALIGNMENT SEQUENCE (ILAS)

The AD9625 must support three different ILAS modes that are

controlled using Bits[3:2] in Register 0x05F as follows:



00: disabled



01: enabled



10: reserved



11: always on test mode

When enabled, the device must also support the capability to

repeat the ILAS using Bits[7:0] in Register 0x062 to determine

the number of times ILAS is repeated (0 = repeat 0 times, ILAS

runs one time only, 1 = repeat one time, ILAS runs twice, and

so forth). Because the number of frames per multiframe is

determined by the value of K, the total number of frames

transmitted during the initial lane alignment sequence is

4 × (K + 1) × (ILAS_COUNT + 1)

where the value of K is defined in Register 0x070, Bits[4:0].

Note that only values divisible by four can be used.

For details about Register 0x05F and Register 0x062, see the

Memory Map Register section.

AD9625 Datasheet(PDF) 46 Page - Analog Devices

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