AD9625 datasheet(65/74 Pages) AD

65 / 74 page

Data Sheet

AD9625

Rev. C | Page 63 of 72

Table 74. JESD204B Configuration Register, Address 0x073 (Default = 0x2F)

Bit No.

Access

Bit Description

[7:5]

JESD204B device subclass version.

0x0: Subclass 0.

0x1: Subclass 1 (default).

0x2: Subclass 2 (not supported).

0x3: undefined.

[4:0]

JESD204B total number of bits per sample (N' = Register 0x073[4:0] + 1).

0x0 to 0xA: unused.

0xB: N' = 12 (L must be equal to 6).

0xC to 0xE: unused.

0xF: N' = 16 (L must be equal to 1, 2, 4, or 8).

Table 75. JESD204B Configuration Register, Address 0x074 (Default = 0x23)

Bit No.

Access

Bit Description

[7:5]

JESD204B version.

0x0: JESD204A. SYNCINB± pins input are internally gated by the frame clock. SYNCINB± must be low for at least

two frame clock cycles to be interpreted as a synchronization request.

0x1: JESD204B. SYNCINB± pins input are internally gated by the local multiframe clock. SYNCINB± must be low

for at least four frame clock cycles to be interpreted as a synchronization request.

0x2 to 0x7: undefined.

[4:0]

JESD204B samples per converter frame cycle (S = Register 0x074[4:0] + 1). These are read-only bits. For the

AD9625, S must be equal to 4 (Register 0x074[4:0] = 3).

Table 76. JESD204B Configuration Register, Address 0x075 (Default = 0x80)

Bit No.

Access

Bit Description

JESD204B high density (HD) format. This is a read-only bit.

0: HD format disabled.

1: HD format enabled. High density mode is automatically enabled based on the values of N' and L.

The values of HD for the AD9625 are as follows:

N' = 16, L = 1, HD = 0.

N' = 16, L = 2, HD = 0.

N' = 16, L = 4, HD = 0.

N' = 12, L = 6, HD = 1.

N' = 16, L = 8, HD = 1 (default).

[6:5]

Unused.

[4:0]

JESD204B Number of control words per frame clock cycle per link (CF). These are read-only bits. For the AD9625,

CF must equal 0 (Register 0x075[4:0] = 0).

Table 77. JESD204B Configuration Register, Address 0x076 (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

JESD204B Serial Reserved Field 1.

Table 78. JESD204B Configuration Register, Address 0x077 (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

JESD204B Serial Reserved Field 2.

Table 79. JESD204B Configuration Register, Address 0x078 (Default = 0xC3)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 0. This value is automatically calculated The value = (the sum of all link

configuration parameters for Lane 0) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

Table 80. JESD204B Configuration Register, Address 0x079 (Default = 0xC4)

Bit No.

Access

Bit Description

[7:0]

JESD204B serial checksum value for Lane 1. This value is automatically calculated. The value = (the sum of all link

configuration parameters for Lane 1) Modulus 256. Checksum is enabled/disabled using Register 0x061, Bit 7.

AD9625 Datasheet(PDF) 65 Page - Analog Devices

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