AD9625 datasheet(69/74 Pages) AD

69 / 74 page

Data Sheet

AD9625

Rev. C | Page 67 of 72

Table 94. Control Register, Address 0x08A (Default = 0x20)

Bit No.

Access

Bit Description

[7:6]

Unused.

[5:4]

Reserved; Bits[5:4] must be set to 10.

[3:2]

Unused.

[1:0]

Bits[1:0] must be set to 00 for LMFC JESD204B alignment with SYSREF±.

Bits[1:0] must be set to 10 for control bit timestamping with SYSREF±.

Table 95. JESD204B Local Multiframe Clock Offset Control Register, Address 0x08B (Default = 0x00)

Bit No.

Access

Bit Description

[7:5]

Unused.

[4:0]

Local multiframe clock (LMFC) phase offset value. These bits provide the reset value for LMFC phase counter when

SYSREF± pins are asserted; this is used for deterministic delay applications.

Table 96. JESD204B Local Frame Clock Offset Control Register, Address 0x08C (Default = 0x00)

Bit No.

Access

Bit Description

[7:0]

Local frame clock phase offset value. Reset value for frame clock phase counter when SYSREF± pins are asserted. For

the AD9625, only values from 0 to 7 are valid. This is used for deterministic delay applications.

Table 97. DIVCLK± Register, Address 0x0F8 (Default = 0x00)

Bit No.

Access

Bit Description

[7:1]

Spare customer register.

0: divide by 4.

1: not used.

Table 98. Reserved Register, Address 0x0F9

Bit No.

Access

Bit Description

[7:0]

Reserved.

Table 99. Customer Spare Register, Address 0x0FF (Default = 0x00)

Bit No.

Access

Bit Description

[7:1]

Unused.

the slave registers.

0: no effect.

1: transfers data from the master registers, written by the register maps, to the slave registers.

Table 100. Interrupt Request (IRQ) Status Register, Address 0x100 (Default = 0x00)

Bit No.

Access

Bit Description

Interrupt request PLL lock error.

1: the PLL is unlocked.

Unused.

Interrupt request SYSREF± hold error.

1: a hold error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register

0x03A.

Interrupt request SYSREF± setup error.

1: a setup error has occurred with the last SYSREF± signal received. To clear this error, set and clear Bit 6 in Register 0x03A.

Unused.

Interrupt request clock error.

AD9625 Datasheet(PDF) 69 Page - Analog Devices

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