PCI9080 datasheet(22/133 Pages) ETC

22 / 133 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 14

Version 0.93

the PCI bus address matching the base address

specified in the PCI Base Address 1 for I/O Mapped

Configuration Register of the PCI 9080.

All PCI read or write accesses to the PCI 9080 registers

can be byte, word or long word accesses. All PCI

memory accesses to the PCI 9080 registers can be

burst or non-burst. The PCI 9080 responds with a PCI

Disconnect for all burst I/O accesses to the PCI 9080

registers.

3.4.2 Local Bus Access to Internal

Registers

The local processor can access all the internal registers

of the PCI 9080 through either internal or external

address decode logic. The PCI 9080 provides an

Address Decode Mode Pin (ADMODE) that selects

whether the internal address decode logic is used or

whether the designer will supply an external chip select

from an external address decoder. Figure 3-2 illustrates

how the dual address decode logic works.

If the Address Decode Mode pin is set to 1, the internal

PCI 9080 address decode logic is enabled. In this mode,

the PCI 9080 internal registers are selected when local

address bits LA[31:29] match input address select pins

S[2:0]. If the Address Decode Mode pin is set to 0, the

PCI 9080 responds to local bus access when S0 is

asserted low through external chip select logic. Note that

S0 must be decoded while ADS# is low.

All local read or write accesses to the PCI 9080 registers

can be byte, word or long word accesses. All local

accesses to the PCI 9080 registers can be burst or non-

burst.

For C and J modes, accesses must be for a 32 bit non-

pipelined bus. The PCI 9080 READYo# indicates a data

transfer is complete.

For S mode, accesses must be for a 16 bit non-

pipelined bus. The PCI 9080 READYo# indicates a data

transfer is complete.

LA31

LA30

LA29

Address Decode Mode Pin

PCI 9080

Internal Register

Chip Select

PCI 9080

Internal Register

Chip Select

PCI 9080

compare

(9080 Chip

Select)

Figure 3-2. Dual Address Decode Mode

3.5 DIRECT DATA TRANSFER MODES

Figure 3-3 and Figure 3-4 illustrate the direct data

transfer modes.

Host CPU

PCI Bus

Local CPU

Host CPU accesses Local Memory or I/O = Direct Slave R/W

Local CPU accesses System Memory = Direct Master R/W

System Memory to Local Memory = DMA R/W

Local

Memory

or I/O

Physical

System

Memory

PLX or

System

Chipset

PLX

Address Translation

DMA, Memory, I/O Cycles

Interrupts

Software Protocol

Figure 3-3. Direct Master, Direct Slave, and DMA

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