PCI9080 datasheet(43/133 Pages) ETC

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SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 35

Version 0.93

interrupt. The interrupt is recorded in the Queue Status

Control (QSR) Register.

From the time that the PCI write transaction is received

until the data is written into local memory and the

Outbound Free Head Pointer Register is incremented,

any PCI direct slave access to the PCI 9080 is issued a

RETRY.

Table 3-5. Circular FIFO Summary

FIFO

Name

PCI

Port

Generate PCI

Interrupt?

Generate Local

Interrupt

Head Pointer

Maintained by

Tail Pointer

Maintained by

Inbound Free

List FIFO

Inbound Queue

Port (Host read)

Local

processor

MU hardware

Inbound Post

List FIFO

Inbound Queue

Port (Host write)

Yes, when Port

is written

MU hardware

Local

processor

Outbound Post

List FIFO

Outbound Queue

Port (Host read)

Yes, when FIFO

is not empty

Local

processor

MU hardware

Outbound Free

List FIFO

Outbound Queue

Port (Host write)

Yes, (LSERR) when

FIFO full

MU hardware

Local

processor

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