PCI9080 datasheet(23/133 Pages) ETC

23 / 133 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 15

Version 0.93

Doorbell Registers set

and clear interrupts

Mailbox Registers can be

read or written from both sides

Used for Passing:

Commands

Pointers

Status

set

clear

set

clear

PCI to Local

Local to PCI

Mailbox 0

Mailbox 1

Mailbox 2

Mailbox 3

Mailbox 4

Mailbox 5

Mailbox 6

Mailbox 7

Figure 3-4. Mailbox/Doorbell Message Passing

3.5.1 Direct Master Operation (Local Master

to PCI Target)

The PCI 9080 supports the direct access of the PCI bus

by either the local processor or an intelligent controller.

Five registers are used to define local to PCI access:

•

Range

•

Local Base Address for Direct Master

to PCI Memory Register

•

Local Base Address for Direct Master

to PCI IO/CFG Register

•

PCI Configuration Address Register

for Direct Master to PCI IO/CFG

•

PCI Base Address

3.5.1.1 Decode

The Range register specifies the local address bits to

use for decoding a Local to PCI access. The local

processor can perform only memory cycles. Therefore,

the Local Base Address for Direct Master to PCI

Memory Register is used to decode an access to PCI

memory space and the Local Base Address for Direct

Master to PCI IO/CFG Register is used to decode an

access to PCI I/O space or PCI bus configuration cycle

access.

3.5.1.2 FIFOs

For Direct Master memory access to the PCI bus, the

PCI 9080 has a 32 Lword (128 byte) write FIFO and a

16 Lword (64 byte) read FIFO. The FIFOs enable the

local bus to operate independently of the PCI bus and

allows high-performance bursting on the local and PCI

buses.

3.5.1.3 Memory Access

The local processor can read or write to the PCI

memory by a read or write to the "Local Base Address

for Direct Master to PCI Memory Register." The PCI

9080 will convert the local read/write access to PCI bus

read/write cycles. The Local Address space starts from

the Direct Master Local Base Address up to the range.

The remap (PCI Base Address) defines the PCI starting

address. (Refer to Example 1 in Section 3.5.2.1).

Writes—The PCI 9080 continues to accept writes and

return READYo# until the write FIFO is full. It then holds

off READYo# until space becomes available in the write

FIFO. A programmable Direct Master FIFO “almost full”

status output is provided (DMPAF#).

Reads—The PCI 9080 holds off READYo# while

gathering an Lword from the PCI bus. Programmable

prefetch modes are available if prefetch is enabled:

prefetch NONE, 4, 8, 16, or continuous until Direct

Master cycle ends. The read cycle is terminated when

the local BLAST# input is asserted. Unused read data is

flushed from the FIFO.

The PCI 9080 does not prefetch read data for single

cycle Direct Master reads (local BLAST# input asserted

during first data phase). In this case, the PCI 9080 reads

a single PCI Lword.

For Direct Master single cycle reads, the PCI 9080

asserts the same PCI bus byte enables as asserted on

the local bus.

For multiple cycle reads, the PCI 9080 reads entire long

words (all PCI byte enables are asserted), regardless of

local byte enables.

3.5.1.4 IO/CFG Access

When a Local Direct Master I/O access to the PCI bus is

made,

the

PCI

Configuration

Address

Configuration

Enable bit

determines

I/O

configuration access is to be made to the PCI bus.

Local burst accesses are broken into single PCI I/O

address/data cycles. The PCI 9080 does not prefetch

read data for I/O and CFG reads.

For Direct Master I/O or Configuration cycles, the PCI

9080 asserts the same PCI bus byte enables as

asserted on the local bus.

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