PCI9080 datasheet(86/133 Pages) ETC

86 / 133 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 78

Version 0.93

4.7 MESSAGING QUEUE REGISTERS

4.7.1 (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register

Table 4-75. (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register

Field

Description

Read

Write

Value after Reset

2:0

Reserved.

Yes

Outbound Post List FIFO Interrupt. This bit is set when the Outbound Post List FIFO

is not empty. This bit is not effected by the interrupt mask bit.

Yes

31:4

Reserved.

Yes

4.7.2 (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register

Table 4-76. (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register

Field

Description

Read

Write

Value after Reset

2:0

Reserved.

Yes

Outbound Post List FIFO Interrupt Mask. Interrupt is masked when this bit is set.

Yes

31:4

Reserved.

Yes

4.7.3 (IQP; PCI:40h) Inbound Queue Port

Table 4-77. (IQP; PCI:40h) Inbound Queue Port

Field

Description

Read

Write

Value after Reset

31:0

Value written by PCI master is stored into the Inbound Post List FIFO, which is located

in local memory at the address pointed to by the Queue Base Address + FIFO Size +

Inbound Post Head Pointer. From the time of the PCI write until the local memory write

and update of the Inbound Post Queue Head Pointer, further accesses to this register

result in a retry. A local interrupt is generated when the Inbound Post List FIFO is not

empty.

When the port is read by the PCI master, the value is read from the Inbound Free List

FIFO, which is located in local memory at the address pointed to by the Queue Base

Address + Inbound Free Tail Pointer. If the FIFO is empty, a value of FFFFFFFh is

returned.

PCI

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