PCI9080 datasheet(7/133 Pages) ETC

7 / 133 page

TABLE OF CONTENTS

©PLX Technology, Inc., 1997

Page vii

Version 0.93

4.6.4 (DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) Register........................................... 73

4.6.5 (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer Register............................................... 73

4.6.6 (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register............................................................... 74

4.6.7 (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register..................................................... 75

4.6.8 (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register ................................................. 75

4.6.9 (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register ........................................... 75

4.6.10 (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register ............................................ 75

4.6.11 (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register ............................................. 76

4.6.12 (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register ............................................. 76

4.6.13 (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register .......................................................................... 76

4.6.14 (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register............................................................................ 77

4.7 MESSAGING QUEUE REGISTERS ..................................................................................................................... 78

4.7.1 (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register ............................................ 78

4.7.2 (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register ............................................. 78

4.7.3 (IQP; PCI:40h) Inbound Queue Port ............................................................................................................... 78

4.7.4 (OQP; PCI:44h) Outbound Queue Port........................................................................................................... 79

4.7.5 (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register ........................................................ 79

4.7.6 (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register ......................................................................... 79

4.7.7 (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register ................................................................ 80

4.7.8 (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register .................................................................. 80

4.7.9 (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register ................................................................ 80

4.7.10 (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register ................................................................. 80

4.7.11 (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register.......................................................... 81

4.7.12 (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register ........................................................... 81

4.7.13 (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register.......................................................... 81

4.7.14 (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register............................................................. 81

4.7.15 (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register.......................................................................... 82

5. PIN DESCRIPTION.................................................................................................................................................... 84

5.1 PIN SUMMARY .................................................................................................................................................... 84

5.2 PINOUT COMMON TO ALL BUS MODES ........................................................................................................... 86

5.3 C BUS MODE PINOUT......................................................................................................................................... 90

5.4 J BUS MODE PINOUT ......................................................................................................................................... 92

5.5 S BUS MODE PINOUT......................................................................................................................................... 94

6. ELECTRICAL SPECIFICATIONS.............................................................................................................................. 96

PCI9080 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

PCI9080 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL