PCI9080 datasheet(68/133 Pages) ETC

68 / 133 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 60

Version 0.93

4.4.5 (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register

Table 4-37. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register

Field

Description

Read

Write

Value after Reset

10:0

Reserved.

Yes

31:11

Specifies which PCI address bits to use for decoding a PCI to local bus expansion

ROM. Each of the bits corresponds to a PCI address bit. Bit 31 corresponds to

Address bit 31. A value of 1 should be written to all bits that should be included in

decode and a 0 to all others (used in conjunction with PCI Configuration register 30h).

Default is 64 KB.

Yes

FFFF00h

4.4.6 (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register

and BREQo Control

Table 4-38. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register and BREQo

Control

Field

Description

Read

Write

Value after Reset

3:0

Direct Slave BREQo (Backoff Request Out) Delay Clocks. Number of local bus clocks

in which a Direct Slave HOLD request is pending and a Local Direct Master access is

in progress and not being granted the bus (LHOLDA) before asserting BREQo. Once

asserted, BREQo remains asserted until the PCI 9080 receives LHOLDA (LSB = 8 or

64 clocks).

Yes

Local Bus BREQo Enable. A value of 1 enables the PCI 9080 to assert the

BREQo output.

Yes

BREQo Timer resolution. A value of 1 changes the LSB of the BREQo timer from 8 to

64 clocks.

Yes

10:6

Reserved.

Yes

31:11

Remap of PCI Expansion ROM space into a Local Address Space. The bits in

this register remap (replace) the PCI address bits used in decode as the local

address bits.

Yes

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