PCI9080 datasheet(77/133 Pages) ETC

77 / 133 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 69

Version 0.93

Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status (continued)

A value of 0 indicates a Direct Master was the bus master during a Master or Target

abort. (Not valid until abort occurs.)

Yes

A value of 0 indicates DMA CH 0 was the bus master during a Master or Target abort.

(Not valid until abort occurs.)

Yes

A value of 0 indicates DMA CH 1 was the bus master during a Master or Target abort.

(Not valid until abort occurs.)

Yes

A value of 0 indicates a Target Abort was generated by the PCI 9080 after

256 consecutive Master retries to a Target. (Not valid until abort occurs.)

Yes

A value of 1 indicates the PCI wrote data to the MailBox #0. Enabled only

if MBOXINTENB is enabled (bit 3 high).

Yes

A value of 1 indicates the PCI wrote data to the MailBox #1. Enabled only

if MBOXINTENB is enabled (bit 3 high).

Yes

A value of 1 indicates the PCI wrote data to the MailBox #2. Enabled only

if MBOXINTENB is enabled (bit 3 high).

Yes

A value of 1 indicates the PCI wrote data to the MailBox #3. Enabled only

if MBOXINTENB is enabled (bit 3 high).

Yes

PCI9080 Datasheet(PDF) 77 Page - List of Unclassifed Manufacturers