PCI9080 datasheet(80/133 Pages) ETC

80 / 133 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 72

Version 0.93

4.6 DMA REGISTERS

4.6.1 (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register

Table 4-62. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register

Field

Description

Read

Write

Value after Reset

1:0

Local Bus Width. A value of 00 indicates a bus width of 8 bits, a value of 01 indicates a

bus width of 16 bits and a value of 10 or 11 indicates a bus width of 32 bits.

Yes

S = 01

J = 11

C = 11

5:2

Internal Wait States (data to data).

Yes

Ready Input Enable. A value of 1 enables Ready input. A value of 0 disables the Ready

input.

Yes

BTERM Input Enable. A value of 1 enables BTERM input. A value of 0 disables the

BTERM input. If this bit is set to 0, the PCI 9080 bursts 4 Lword maximum at a time.

Yes

Local Burst Enable. A value of 1 enables bursting. A value of 0 disables local bursting.

If burst is disabled, the local bus performs continuous single cycles for burst PCI

read/write cycles.

Yes

Chaining. A value of 1 indicates chaining mode is enabled. For chaining mode, the

DMA source address, destination address and byte count are loaded from memory in

PCI or local address spaces. A value of 0 indicates nonchaining mode is enabled.

Yes

Done Interrupt Enable. A value of 1 enables interrupt when done. A value of 0 disables

interrupt when done. If the DMA Clear Count Mode is enabled, the interrupt won’t

occur until the byte count is cleared.

Yes

Local Addressing Mode. A value of 1 indicates local address LA[31:2] to be held

constant. A value of 0 indicates local address is incremented.

Yes

Demand Mode. A value of 1 causes the DMA controller to operate in demand mode. In

demand mode the DMA controller transfers data when its DREQ# input is asserted. It

asserts DACK# to indicate the current local bus transfer is in response to the DREQ#

input. The DMA controller transfers Lwords (32 bits) of data. This may result in

multiple transfers for an 8- or 16-bit bus.

Yes

Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9080 performs

Write and Invalidate cycles to the PCI bus. The PCI 9080 supports Write and

Invalidate sizes of 8 or 16 Lwords. The size is specified in the PCI Cache Line Size

rather than Write and Invalidate transfers. Transfers must start and end at the Cache

Line Boundaries.

Yes

DMA EOT (End of Transfer) Enable. A value of 1 enables the EOT input pin. A value

of 0 disables the EOT input pin.

Yes

DMA Stop Data Transfer Mode. A value of 0 sends a BLAST to terminate DMA

transfer. A value of 1 indicates an EOT asserted or DREQ# negated during demand

mode DMA terminates the DMA transfer.

Yes

DMA Clear Count Mode. When set to 1, the byte count in each chaining descriptor, if it

is in local memory, is cleared when the corresponding DMA transfer is complete.

Note: If chaining descriptor is in PCI memory, the count will not be cleared.

Yes

DMA Channel 0 Interrupt Select. A value of 1 routes the DMA Channel 0 interrupt to

the PCI interrupt. A value of 0 routes the DMA Channel 0 interrupt to the local bus

interrupt.

Yes

31:18

Reserved.

Yes

PCI9080 Datasheet(PDF) 80 Page - List of Unclassifed Manufacturers

PCI9080 Datasheet(HTML) 80 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL