PCI9080 datasheet(11/133 Pages) ETC

11 / 133 page

SECTION 1

PCI 9080

GENERAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 3

Version 0.93

1.2 MAJOR FEATURES

PCI 2.1 Compliant. The PCI 9080 is compliant with all

aspects of PCI specification version 2.1.

I2O Messaging Unit. The PCI 9080 incorporates an I2O

messaging unit. This enables the adapter or embedded

system

communicate

with

other

I2O-supported

devices. The I2O messaging unit is fully compatible with

the PCI extension of the I2O Version 1.5 specification.

Dual Independent Programmable DMA Controllers

with Bidirectional FIFOs. The PCI 9080 provides two

independently

programmable

DMA

controllers

with

bidirectional FIFOs for each channel. Each channel

supports both nonchaining and chaining DMA modes

and demand mode DMA, and End of Transfer (EOT)

mode.

Direct Bus Master. The PCI 9080 supports both

memory mapped burst transfer accesses and I/O

mapped single transfer accesses to the PCI bus from

the Local Bus Master. The PCI 9080 also supports PCI

bus interlock (“LOCK#”) cycles. Bidirectional FIFOs for

both Read- and Write-enable high-performance bursting

on the local and PCI buses.

PCI Host Capability. In direct master mode, the PCI

9080 can generate Type 0 or Type 1 PCI configuration

cycles.

Direct Slave. The PCI 9080 supports both memory

mapped and I/O mapped burst accesses to PCI bus

from the Local Bus Master. Bidirectional FIFOs for both

Read- and Write-enable high-performance bursting on

the local and PCI buses.

Programmable Local Bus Modes. The PCI 9080 is a

PCI bus master interface chip that connects a PCI bus

to one of three local bus types, selected through mode

pins. The PCI 9080 may be connected to any local bus

with a similar design with little or no glue logic. Table 1-

1 lists the three modes.

Table 1-1. Programmable Local Bus Modes

Mode

Description

32-bit address/32-bit data, nonmultiplexed

32-bit address/32-bit data, multiplexed

32-bit address/16-bit data, multiplexed

Interrupt Generator. The PCI 9080 can generate PCI

and local interrupts from several sources.

Clock. The PCI 9080 local bus interface runs from a

local TTL clock and generates the necessary internal

clocks. This clock runs asynchronously to the PCI clock.

There is a buffered PCI clock (BPCLKo) for the local

side to use. BPCLKo may be connected to LCLK.

3.3 Volt and 5 Volt Operation. The 9080 provides

either 3.3 Volt or 5 Volt signaling on the PCI bus.

A 3.3 V signaling environment requires 5 V and 3.3 V

VCC. A 5 V PCI bus and local bus environment requires

5 V VCC.

Serial EEPROM Interface. The PCI 9080 contains an

optional serial EEPROM interface that can be used to

load configuration information. This is useful for loading

information that is unique to a particular adapter (such

as Network ID or Vendor ID).

Mailbox Registers. The PCI 9080 contains eight 32 bit

mailbox registers that may be accessed from either the

PCI or the local bus.

Doorbell Registers. The PCI 9080 includes two 32 bit

doorbell registers. One generates interrupts from the

PCI bus to the local bus. The other generates interrupts

from the local bus to the PCI bus.

Unaligned DMA Transfer Support. The PCI 9080 can

transfer data on any byte boundary.

Big/Little Endian Conversion. The PCI 9080 supports

dynamic switching between Big Endian and Little Endian

operations for Direct Slave, Direct Master, DMA, and the

internal register accesses on the local side.

Note: PCI Bus is always Little Endian.

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